From nobody Thu Oct 2 15:34:57 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A13BC2FFDF6; Thu, 2 Oct 2025 09:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759397832; cv=none; b=jJOlaLcgJBp/KVQ/lGcThtTSpxFMdMmoCEVhOPZT/LGj+U/IyUdS9WKcGaT/QiceCsHfxW4kk2ZzR9lhpMWJBhuS2HsxBjzxY/IN8ReY8zG35YY9lgMGO8Ri2/iR3cpAxUTZpMnfFF60xAOfOECISTzYtLgcKwTnXLsAdybaP40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759397832; c=relaxed/simple; bh=sPvcV9MoYnQ/udriV5D5gjdJxnV9P7IjNVeVqPp7m4U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D4XqRcD/v7/g4UDS5NF8IQIpuU2vE6LvoKVdwPNKx9W6OX9dCNmOBSwyYFNS48+e+6IVXOUquLJ7swQ+j4YqaHT7iAmSHa9jX3aYb1h/XbHpfyyrgrjXTcioUpWUIlJEDAVwLDUdxAMBIv9kVxeAnFbbvrHLjY0Lm6prGjKBBHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lG/BNyD0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lG/BNyD0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1759397828; bh=sPvcV9MoYnQ/udriV5D5gjdJxnV9P7IjNVeVqPp7m4U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lG/BNyD0cJf2lEC3hOoxPpDw96dJdM1h0gKotK+kY9XsOPaxUI6aSnM7OGmHuNeFP No4MJFkGaWApZpRg6cN6NTIi3AZrpfJPWxoBVAS+Dg0qnhKYG01bk3BsOA3z2jHYZ9 9jSNZzfsULaKhmtI5zbBEb1fUx7vSHYc2+/zz1ahfB9KqnHvHZLxv4pTO4OGxkp7pZ cLnVrjb3SABFkFVbRbOZD5Q3u+0uecS1HDSiz8EVviVETAg5d4Z4nccbrc+fKYHrRi v1HWWiL8rJBaKzYMqtkZRllQEN6j7Ly1dpT+TsfR9G7ppvBmOm0/uG6jnEBq4wYjZX 0Sj3/q52QgcoA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id F060E17E12DA; Thu, 2 Oct 2025 11:37:07 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Sebastian Reichel , Neil Armstrong Subject: [PATCH v5 3/7] power: reset: qcom-pon: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Thu, 2 Oct 2025 11:36:53 +0200 Message-ID: <20251002093657.2055332-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251002093657.2055332-1-angelogioacchino.delregno@collabora.com> References: <20251002093657.2055332-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrates a Power On device supporting pwrkey and resin along with the Android reboot reason action identifier. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for PON and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Reviewed-by: Sebastian Reichel Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/power/reset/qcom-pon.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c index 7e108982a582..0e075a2e5e48 100644 --- a/drivers/power/reset/qcom-pon.c +++ b/drivers/power/reset/qcom-pon.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #define PON_SOFT_RB_SPARE 0x8f =20 @@ -22,7 +23,6 @@ struct qcom_pon { struct device *dev; struct regmap *regmap; - u32 baseaddr; struct reboot_mode_driver reboot_mode; long reason_shift; }; @@ -35,7 +35,7 @@ static int qcom_pon_reboot_mode_write(struct reboot_mode_= driver *reboot, int ret; =20 ret =3D regmap_update_bits(pon->regmap, - pon->baseaddr + PON_SOFT_RB_SPARE, + PON_SOFT_RB_SPARE, GENMASK(7, pon->reason_shift), magic << pon->reason_shift); if (ret < 0) @@ -46,27 +46,42 @@ static int qcom_pon_reboot_mode_write(struct reboot_mod= e_driver *reboot, =20 static int qcom_pon_probe(struct platform_device *pdev) { + struct regmap_config qcom_pon_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct device *dev =3D &pdev->dev; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct qcom_pon *pon; long reason_shift; int error; =20 + if (!dev->parent) + return -ENODEV; + pon =3D devm_kzalloc(&pdev->dev, sizeof(*pon), GFP_KERNEL); if (!pon) return -ENOMEM; =20 pon->dev =3D &pdev->dev; =20 - pon->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); - if (!pon->regmap) { - dev_err(&pdev->dev, "failed to locate regmap\n"); - return -ENODEV; - } + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); =20 - error =3D of_property_read_u32(pdev->dev.of_node, "reg", - &pon->baseaddr); + error =3D of_property_read_u32(dev->of_node, "reg", + &qcom_pon_regmap_config.reg_base); if (error) return error; =20 + pon->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &qcom_pon_regm= ap_config); + if (IS_ERR(pon->regmap)) + return PTR_ERR(pon->regmap); + reason_shift =3D (long)of_device_get_match_data(&pdev->dev); =20 if (reason_shift !=3D NO_REASON_SHIFT) { @@ -106,3 +121,4 @@ module_platform_driver(qcom_pon_driver); =20 MODULE_DESCRIPTION("Qualcomm Power On driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0