From nobody Thu Oct 2 15:34:57 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C0012F5326; Thu, 2 Oct 2025 09:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759397831; cv=none; b=d4sM+bI+CBt8b1srxaTTBCMeHI+I/8ApTCruyIG9OW9622G2E0MSnajD32GVEGwhk91QtT2PPtqBy+TZYwKhFdfNfGlQX9ByntlwYwWCJXFhJqYO6JUQ7PM3y77N3Fknv+o4p2NqKy6hbDEDf7seyGVj+9Wim7wh2XLRbbBUb/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759397831; c=relaxed/simple; bh=1otmjcp+8VLOXwHsEjahxbfe6VDNDKXcrtdoOgcHKqw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cf7x+DdlCxMgByMS8fjL3wBX9/G6+QrUwC8NuWFIn2uQIsKCSwR/yT7YyAH/D9svFw2mKGTOhsDL/5lMRM/CjcSWjTz3Dhb9dZN84kRsDHI04RU2I25AHlTRbW6yKbjZ3KtmS+YxyIBViuNU2Yhu88sD3yBZdPhpyN8yV3LrPgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QjVX03SM; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QjVX03SM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1759397827; bh=1otmjcp+8VLOXwHsEjahxbfe6VDNDKXcrtdoOgcHKqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QjVX03SMsICILOGDzo40xTG5tnUKpAZ8H+BOrjoiEwt9pge+XEp+9Ic5RX/TB7UgY F7bwbkAYqTmLvFYXRHZXYrmHozVrA7B32lRUTGWmkP6UbgbTOrPqE7d0q0F3YC6Fum UNUWHauEqtJBAD9yck+ad+V+nZAZNjNhI07RmTNwF5qwA/iMQxav2u+uZjtUIwkl5V DqFR7DyJbXFfqW4wrGNyT8HwXhg4AVHdjR7m6NDn1e9CIEdD91ghwn/F7zkR57QaiS ZYh3tzxvCqSHn0JLpnIwBj4GkYkhg3DWIv01NNOMbWuO/EbcQsq1t1yaM/iNcF3B9l RUCULQo3cHETw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id E207517E12C4; Thu, 2 Oct 2025 11:37:06 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Konrad Dybcio , Neil Armstrong Subject: [PATCH v5 2/7] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Thu, 2 Oct 2025 11:36:52 +0200 Message-ID: <20251002093657.2055332-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251002093657.2055332-1-angelogioacchino.delregno@collabora.com> References: <20251002093657.2055332-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrate a SDAM device, internally located in a specific address range reachable through SPMI communication. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device for SDAM and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Reviewed-by: Konrad Dybcio Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: AngeloGioacchino Del Regno --- drivers/nvmem/Kconfig | 1 + drivers/nvmem/qcom-spmi-sdam.c | 36 +++++++++++++++++++++++----------- 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index e0d88d3199c1..23858269b61f 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -359,6 +359,7 @@ config NVMEM_SNVS_LPGPR config NVMEM_SPMI_SDAM tristate "SPMI SDAM Support" depends on SPMI + select REGMAP_SPMI help This driver supports the Shared Direct Access Memory Module on Qualcomm Technologies, Inc. PMICs. It provides the clients diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c index 4f1cca6eab71..2bb7b3bc497e 100644 --- a/drivers/nvmem/qcom-spmi-sdam.c +++ b/drivers/nvmem/qcom-spmi-sdam.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define SDAM_MEM_START 0x40 #define REGISTER_MAP_ID 0x40 @@ -20,7 +21,6 @@ struct sdam_chip { struct regmap *regmap; struct nvmem_config sdam_config; - unsigned int base; unsigned int size; }; =20 @@ -73,7 +73,7 @@ static int sdam_read(void *priv, unsigned int offset, voi= d *val, return -EINVAL; } =20 - rc =3D regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes); + rc =3D regmap_bulk_read(sdam->regmap, offset, val, bytes); if (rc < 0) dev_err(dev, "Failed to read SDAM offset %#x len=3D%zd, rc=3D%d\n", offset, bytes, rc); @@ -100,7 +100,7 @@ static int sdam_write(void *priv, unsigned int offset, = void *val, return -EINVAL; } =20 - rc =3D regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes); + rc =3D regmap_bulk_write(sdam->regmap, offset, val, bytes); if (rc < 0) dev_err(dev, "Failed to write SDAM offset %#x len=3D%zd, rc=3D%d\n", offset, bytes, rc); @@ -110,8 +110,17 @@ static int sdam_write(void *priv, unsigned int offset,= void *val, =20 static int sdam_probe(struct platform_device *pdev) { + struct regmap_config sdam_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; struct sdam_chip *sdam; struct nvmem_device *nvmem; + struct spmi_device *sparent; + struct spmi_subdevice *sub_sdev; + struct device *dev =3D &pdev->dev; unsigned int val; int rc; =20 @@ -119,19 +128,23 @@ static int sdam_probe(struct platform_device *pdev) if (!sdam) return -ENOMEM; =20 - sdam->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); - if (!sdam->regmap) { - dev_err(&pdev->dev, "Failed to get regmap handle\n"); - return -ENXIO; - } + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); =20 - rc =3D of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base); + rc =3D of_property_read_u32(dev->of_node, "reg", &sdam_regmap_config.reg_= base); if (rc < 0) { dev_err(&pdev->dev, "Failed to get SDAM base, rc=3D%d\n", rc); return -EINVAL; } =20 - rc =3D regmap_read(sdam->regmap, sdam->base + SDAM_SIZE, &val); + sdam->regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &sdam_regmap_= config); + if (IS_ERR(sdam->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(sdam->regmap), + "Failed to get regmap handle\n"); + + rc =3D regmap_read(sdam->regmap, SDAM_SIZE, &val); if (rc < 0) { dev_err(&pdev->dev, "Failed to read SDAM_SIZE rc=3D%d\n", rc); return -EINVAL; @@ -159,7 +172,7 @@ static int sdam_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "SDAM base=3D%#x size=3D%u registered successfully\n", - sdam->base, sdam->size); + sdam_regmap_config.reg_base, sdam->size); =20 return 0; } @@ -181,3 +194,4 @@ module_platform_driver(sdam_driver); =20 MODULE_DESCRIPTION("QCOM SPMI SDAM driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0