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Thu, 2 Oct 2025 02:01:30 -0700 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v2 3/4] memory: tegra: Add support for multiple irqs Date: Thu, 2 Oct 2025 09:00:53 +0000 Message-ID: <20251002090054.1837481-4-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251002090054.1837481-1-ketanp@nvidia.com> References: <20251002090054.1837481-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|SA1PR12MB6993:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b97e459-6b98-4e1b-62c0-08de01924dc3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?cJoPOqwQcXrSCGu1YBEFGXU/e4emauvey7Rlmp3iB8fSP/sRb/OE3S3SHjAC?= =?us-ascii?Q?bM3N15BVHGBJKPQmUvr+WBdprVQap2eN6RrHEEs1hEel171LjpgI+KM7ntF8?= =?us-ascii?Q?ppgtePX/EaXhPMeK9U7mI0vj7iZ8d8a/BhIwUhyHYSNivwqly1ACv+SDfteA?= =?us-ascii?Q?vOEsT0czhJapFzBLtQ9ZiGTl8Mxr427lqA8EB85u6jd+bs5rJ8pqhskdITUM?= =?us-ascii?Q?1J6Cm3rOM5wSxnNoN6fhJ0CPAlCV+EUk7miXASMxWCAeORvnlega6Klflfka?= =?us-ascii?Q?4XZpRdpzz+fcBXhNK8R281itrOd2pdMl7cJpFVbLWUc2gJG6HSldggE+Ou/a?= =?us-ascii?Q?etPjZSYHLyCgD4DP92vVjLUfkT2Z0iOjqs9RLGKbIVnF2ORGuZkxcQj6w+iv?= =?us-ascii?Q?rfsXECmZ4Bb0mz+kw0Ra4JwVYHZ0huHbyTAvdOPxMCucb1SLbVxGKx/Gucif?= =?us-ascii?Q?H3pDhDWop/2vbI2mibY3byOA6sYUHLE6LEJjYY60sP8tOLfpwgTnCIMGPHtc?= =?us-ascii?Q?RCuFmz9sJh5c3iRlSoErsUKfD4xLaBfSjSm5r5Itc9MPq1W2Qb+FX46strlA?= =?us-ascii?Q?hyVQW+4Ei9K/78VdA56TDhzmF89dtVpNv/Owc9mdIavr5usDa+l1Xn5Q3Efa?= =?us-ascii?Q?Ewm5uXYQ4ADflujUEt1PckJYLJrx2d2cS0rq1EefcVYxWYPbwEstVO2DibId?= =?us-ascii?Q?gCWrzIT5t7O9OuRQlrsb+GfMEQRTW3wgu3PsRr7WN3Z9no+SI1XFq074PKmD?= =?us-ascii?Q?/5qhZQWyjZQTLV79eooOHLt99Ev17d08HsLg+6674h89F8d5p544LkOUCjzL?= =?us-ascii?Q?KD89BLnr6LsJ5lrtpsLyKmKPniAle8BgLZwcAF6HeFj8+z9e51AUYb06brRs?= =?us-ascii?Q?G09obmDtPU5hyYrx6mu3lAj0OdKdhBqTj2C0V/9ESadimLEJoiS7m9+lI8LA?= =?us-ascii?Q?FQcBf4kgswhwrFiISUsvki/LrWk7NnJ46cJK6Dxu0kxqPBftPKApB+e21xWy?= =?us-ascii?Q?+WIygSRUGb3zd3qX71jfXeNgcTx1VoTbkxKGiTbZQDah4ujpqUOq25Wjo/eS?= =?us-ascii?Q?ZXR424ji+s8ChsU34PhoCuDv6hIFL2wq+/Y0FDtNVXJx4apJcuanaOHEPKKf?= =?us-ascii?Q?lMdXbE4tEM9krSx/cDietGr9TVamvK1rXE55y75FIUFp30oFRDrxoN9f9aeV?= =?us-ascii?Q?hTVfkOaAjL0BJHBafLuqJd5wPFOHZsjBNYx6SnAOvQgnoxU55NJiZS9vKOa4?= =?us-ascii?Q?BF2PrvwJgU4IjG8OUvkmmyXoaBBfR3cc8N3yd9NfuHuBl5Fkfjd0I0xlVYHa?= =?us-ascii?Q?UkWVfrNP4iu785GQkBbtrQbb0LskH0zoljtYlYCABsOHAF3wMxfbjnwgEmRS?= =?us-ascii?Q?m10yvE6HYz0cIpeyrgkgNNqUPHsr4iKeqWLf8g6uGaB/XdpNoy6uFgKM7bx3?= =?us-ascii?Q?ERSr2JlAQ9f1KYFR8PBfqG+yxMMiL8HUjzvGNK8EbzbWGUFgq+E9reZBOtj4?= =?us-ascii?Q?Ij5sXmfHg2p4461BM9UDZRAI4WbDA456SUfzZU71oEm8bXpLGCsQl5VJZIIk?= =?us-ascii?Q?wDRR4GpfLr2gckQVqAg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2025 09:01:41.3333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b97e459-6b98-4e1b-62c0-08de01924dc3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6993 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to handle multiple MC interrupts lines as the number of interrupt lines could vary based upon SoC. Add field to specify the number of interrupts and iterate over the number of interrupts to register handler for each interrupt. SoC with multiple interrupts will be added in subsequent patches. Signed-off-by: Ketan Patil --- drivers/memory/tegra/mc.c | 35 +++++++++++++++++++++------------ drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra20.c | 7 ++++++- include/soc/tegra/mc.h | 4 +++- 5 files changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 6c1578b25a61..03cf49165439 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -549,9 +549,14 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } =20 +const irq_handler_t tegra30_mc_irq_handlers[] =3D { + tegra30_mc_handle_irq +}; + const struct tegra_mc_ops tegra30_mc_ops =3D { .probe =3D tegra30_mc_probe, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D 1, }; #endif =20 @@ -953,25 +958,29 @@ static int tegra_mc_probe(struct platform_device *pde= v) tegra_mc_num_channel_enabled(mc); =20 if (mc->soc->ops && mc->soc->ops->handle_irq) { - mc->irq =3D platform_get_irq(pdev, 0); - if (mc->irq < 0) - return mc->irq; - WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); =20 + for (int i =3D 0; i < mc->soc->ops->num_interrupts; i++) { + int irq; + + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + err =3D devm_request_irq(&pdev->dev, irq, mc->soc->ops->handle_irq[i], = 0, + dev_name(&pdev->dev), mc); + if (err < 0) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, + err); + return err; + } + } + if (mc->soc->num_channels) mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, MC_INTMASK); else mc_writel(mc, mc->soc->intmask, MC_INTMASK); - - err =3D devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, = 0, - dev_name(&pdev->dev), mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, - err); - return err; - } } =20 if (mc->soc->reset_ops) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 482f836f7816..06ae3dd37a47 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -194,6 +194,7 @@ extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); +extern const irq_handler_t tegra30_mc_irq_handlers[]; extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; =20 diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index a30158d92412..a3727fc383ac 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -174,7 +174,8 @@ const struct tegra_mc_ops tegra186_mc_ops =3D { .remove =3D tegra186_mc_remove, .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D 1, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 46e97bb10163..75eeb49054cc 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -761,9 +761,14 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void= *data) return IRQ_HANDLED; } =20 +static const irq_handler_t tegra20_mc_irq_handlers[] =3D { + tegra20_mc_handle_irq +}; + static const struct tegra_mc_ops tegra20_mc_ops =3D { .probe =3D tegra20_mc_probe, - .handle_irq =3D tegra20_mc_handle_irq, + .handle_irq =3D tegra20_mc_irq_handlers, + .num_interrupts =3D 1, }; =20 const struct tegra_mc_soc tegra20_mc_soc =3D { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d11dfefbe551..4a2cadbc0084 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 struct clk; struct device; @@ -164,8 +165,9 @@ struct tegra_mc_ops { int (*probe)(struct tegra_mc *mc); void (*remove)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); - irqreturn_t (*handle_irq)(int irq, void *data); + const irq_handler_t *handle_irq; int (*probe_device)(struct tegra_mc *mc, struct device *dev); + unsigned int num_interrupts; }; =20 struct tegra_mc_regs { --=20 2.17.1