From nobody Wed Dec 17 16:24:51 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 542A725784A for ; Thu, 2 Oct 2025 03:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759376310; cv=none; b=qJjs7M4LvWuuToPimADBFfDRrSALMTsoj0ZbW66KtC8+GuULvEzprFOtev3Hqm507xrb3IpMQwzX0hZAbV1kCNNEVphdCMV7I2XFAZPS0W5/3Q7u2skf5aMGOTAWbrnjAzYRUdLZbL5ElRlYDNnDSbsDyoNagEyg9MCc+F+9qaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759376310; c=relaxed/simple; bh=lq2ExnNqIsCf2nA3TdJVLqxRe4VyShlFupZuLdV9cvI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=JyAIYFLAA8LEkKVOFbVGfAt9hnJlmyCCFKbNR33xO7TZVy2AXGLgSXzPv6IMniB6MgTgmF7VldhvvDAjL0cFc71YaySSPiuBR6dgP/frveLb1im5+fxpwFEoCa9ksXg9me9u3V0G/OIoDhhm7CmxQad1ayHbmmSiHLqSfjywxVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5923YIBN012646 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 2 Oct 2025 11:34:18 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Thu, 2 Oct 2025 11:34:18 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , Hui Min Mina Chou , Ben Zong-You Xie Subject: [PATCH] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries Date: Thu, 2 Oct 2025 11:34:02 +0800 Message-ID: <20251002033402.610651-1-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5923YIBN012646 From: Hui Min Mina Chou If multiple VCPUs of the same Guest/VM run on the same Host CPU, hfence.vvma only flushes that Host CPU=E2=80=99s VS-stage TLB. Other Host C= PUs may retain stale VS-stage entries. When a VCPU later migrates to a different Host CPU, it can hit these stale GVA to GPA mappings, causing unexpected faults in the Guest. To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU. This ensures that no stale VS-stage mappings remain after VCPU migration. Fixes: b79bf2025dbc ("RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sani= tize()") Signed-off-by: Hui Min Mina Chou Signed-off-by: Ben Zong-You Xie Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/kvm/vmid.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c index 3b426c800480..38c6f532a6f8 100644 --- a/arch/riscv/kvm/vmid.c +++ b/arch/riscv/kvm/vmid.c @@ -146,4 +146,10 @@ void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *v= cpu) =20 vmid =3D READ_ONCE(vcpu->kvm->arch.vmid.vmid); kvm_riscv_local_hfence_gvma_vmid_all(vmid); + + /* + * Flush VS-stage TLBs entry after VCPU migration to avoid using + * stale entries. + */ + kvm_riscv_local_hfence_vvma_all(vmid); } --=20 2.34.1