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Thu, 02 Oct 2025 03:09:58 -0700 (PDT) From: James Clark Date: Thu, 02 Oct 2025 11:09:32 +0100 Subject: [PATCH v3 4/5] coresight: Add format attribute for setting the timestamp interval Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251002-james-cs-syncfreq-v3-4-fe5df2bf91d1@linaro.org> References: <20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@linaro.org> In-Reply-To: <20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@linaro.org> To: Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Timestamps are currently emitted at the maximum rate possible, which is much too frequent for most use cases. Add an attribute to be able to set the interval. Granular control is not required, so save space in the config by interpreting it as 2 ^ ts_interval. And then 4 bits (0 - 15) is enough to set the interval to be larger than the existing SYNC timestamp interval. No sysfs file is needed for this attribute because counter generated timestamps are only configured for Perf mode. Only show this attribute for ETM4x because timestamps aren't configured in the same way for ETM3x. The attribute is only ever read in coresight-etm4x-core.c. Reviewed-by: Leo Yan Tested-by: Leo Yan Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 +++++++++++++++- drivers/hwtracing/coresight/coresight-etm-perf.h | 7 +++++++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 21 ++++++++++++------= --- 3 files changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index f677c08233ba..0c1b990fc56e 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -69,7 +70,8 @@ PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); - +/* Interval =3D (2 ^ ts_level) */ +GEN_PMU_FORMAT_ATTR(ts_level); =20 /* * contextid always traces the "PID". The PID is in CONTEXTIDR_EL1 @@ -103,11 +105,23 @@ static struct attribute *etm_config_formats_attr[] = =3D { &format_attr_configid.attr, &format_attr_branch_broadcast.attr, &format_attr_cc_threshold.attr, + &format_attr_ts_level.attr, NULL, }; =20 +static umode_t etm_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int unused) +{ + if (attr =3D=3D &format_attr_ts_level.attr && + !IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)) + return 0; + + return attr->mode; +} + static const struct attribute_group etm_pmu_format_group =3D { .name =3D "format", + .is_visible =3D etm_format_attr_is_visible, .attrs =3D etm_config_formats_attr, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwt= racing/coresight/coresight-etm-perf.h index 5febbcdb8696..d2664ffb33e5 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_ETM_PERF_H #define _CORESIGHT_ETM_PERF_H =20 +#include #include #include "coresight-priv.h" =20 @@ -20,6 +21,12 @@ struct cscfg_config_desc; */ #define ETM_ADDR_CMP_MAX 8 =20 +#define ATTR_CFG_FLD_ts_level_CFG config3 +#define ATTR_CFG_FLD_ts_level_LO 12 +#define ATTR_CFG_FLD_ts_level_HI 15 +#define ATTR_CFG_FLD_ts_level_MASK GENMASK(ATTR_CFG_FLD_ts_level_HI, \ + ATTR_CFG_FLD_ts_level_LO) + /** * struct etm_filter - single instruction range or start/stop configuratio= n. * @start_addr: The address to start tracing on. diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 920d092ef862..034844f52bb2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -616,7 +617,7 @@ static void etm4_enable_hw_smp_call(void *info) * +--------------+ * | * +------v-------+ - * | Counter x | (reload to 1 on underflow) + * | Counter x | (reload to 2 ^ ts_level on underflow) * +--------------+ * | * +------v--------------+ @@ -627,11 +628,17 @@ static void etm4_enable_hw_smp_call(void *info) * | Timestamp Generator | (timestamp on resource y) * +----------------------+ */ -static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, + struct perf_event_attr *attr) { int ctridx; int rselector; struct etmv4_config *config =3D &drvdata->config; + u8 ts_level =3D ATTR_CFG_GET_FLD(attr, ts_level); + + /* Disable when ts_level =3D=3D MAX */ + if (ts_level =3D=3D FIELD_GET(ATTR_CFG_FLD_ts_level_MASK, UINT_MAX)) + return 0; =20 /* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) @@ -667,12 +674,8 @@ static int etm4_config_timestamp_event(struct etmv4_dr= vdata *drvdata) return -ENOSPC; } =20 - /* - * Initialise original and reload counter value to the smallest - * possible value in order to get as much precision as we can. - */ - config->cntr_val[ctridx] =3D 1; - config->cntrldvr[ctridx] =3D 1; + /* Initialise original and reload counter value. */ + config->cntr_val[ctridx] =3D config->cntrldvr[ctridx] =3D 1 << ts_level; =20 /* * Trace Counter Control Register TRCCNTCTLRn @@ -762,7 +765,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, * order to correlate instructions executed on different CPUs * (CPU-wide trace scenarios). */ - ret =3D etm4_config_timestamp_event(drvdata); + ret =3D etm4_config_timestamp_event(drvdata, attr); =20 /* * No need to go further if timestamp intervals can't --=20 2.34.1