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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58b0119e60fsm884712e87.94.2025.10.02.07.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 07:42:17 -0700 (PDT) From: Marcus Folkesson Date: Thu, 02 Oct 2025 16:41:36 +0200 Subject: [PATCH v2 5/5] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251002-i2c-mux-v2-5-b698564cd956@gmail.com> References: <20251002-i2c-mux-v2-0-b698564cd956@gmail.com> In-Reply-To: <20251002-i2c-mux-v2-0-b698564cd956@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8215; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=RcFIrKoSgnto39HXDCzkc41AKHrLdxTXBU7nIzeA4ck=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo3o89diRzxaElr4YwuimquAd0U3fRuYUfF6kui ED5Vph5J1CJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaN6PPQAKCRCIgE5vWV1S MkfmD/92ZWCqZ+QbeUVymKqEGOTxJKzOoYBSjuURXjqmGPk0f0frTtk7kloYMLTIVVzB1zxwJh/ vBq4l6zRtFShK/uC42KCcnZ7tKup/o9D9IJxO8KBECwFjn08HowEAP8+EsBP0LiL4qrMrcHjZSM qNJd+njT7tz+IOxrYeDxJyC4XYNcoagRR09VsoJGdBp0oKHNUr+fsqiUwLriErQrBbXN00xId4l 9FQ7qiwiAuUSN8r/3EOMRUFKBJr7CJA0q2t6ImDhT5wGMCOkdt9xjrgXHd2EuG8NVayOtIVLJW+ L1/99h62x3xYWbf806rrwdvzUBJ6XTGlSeAMOhNR08Uu15egDxcyU+f7x3+wDLd24HpTLqy/biK JJPwATk8+qUgJtOBve9DUG1ApYnk9vUnxwlcmpmeR5buV9uwaM9R1plIxEnAemVNADW0zIlweKN wwjJejhCDwmb+ztMoxZ4XN/R3kyqXXMJOftsFoN52ETBLHZDTtvlj2XzHWs/xmHZPsBqDKk5To+ ZPEn/G3Yil9tf0QuQhMVXbWVx+jx/j9d+fEnwtsu/T6N17u9SMiPWBjHInSXfjBBalVEXYctDyM JX9htBROmH5/E/pgtErT+JcsmdshvrWE9TmP7M6SCA0ZDepW+trMReOwtdf7mcnfdXRkqDRwCj8 OHStS1HZ5zBHzhg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 176 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 176 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-top= ology.rst index 48fce0f7491bf1bcd4a851f685b010386c9ce0d2..2c4a1364ce82e353f51608e60d0= 8535f80523fea 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,182 @@ When D1 or D2 are accessed, accesses to D3 and D4 are= locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. =20 +Bus Speed and I2C Multiplexers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +I2C bus multiplexers allows multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therfor changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affect= ed +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D2 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be is set to 400kHz, a speed that D2 may not su= pport. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the mult= iplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any ot= her devices +and many of the caveats are avoided. + +Other multiplexers in parallell is still okay as those are locked out duri= ng transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between t= he +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +is supposed to be. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, whi= ch +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, whi= ch +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallell +---------------------------- + +When multiple muxes are used in parallell all access to other muxes are lo= cked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-desele= ct for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels is put into when= no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are p= referred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devi= ces that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: +- All channels disconnected: No problem, D1 and D2 are not affected by com= munication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High= speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem, if the predefined channel D1. Set predefine= d channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writint, the following controllers has support: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +i2c-davinci Supports dynamic bus speed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Mux type of existing device drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.50.1