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Wed, 1 Oct 2025 08:02:25 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v3 7/8] cpufreq: CPPC: update policy min/max when toggling auto_select Date: Wed, 1 Oct 2025 20:31:03 +0530 Message-ID: <20251001150104.1275188-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001150104.1275188-1-sumitg@nvidia.com> References: <20251001150104.1275188-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|CH3PR12MB9170:EE_ X-MS-Office365-Filtering-Correlation-Id: 5cb7c61f-6e28-419a-e307-08de00fb9902 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 15:02:53.5118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5cb7c61f-6e28-419a-e307-08de00fb9902 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9170 Content-Type: text/plain; charset="utf-8" When CPPC autonomous selection (auto_select) is enabled or disabled, the policy min/max frequency limits should be updated appropriately to reflect the new operating mode. Currently, toggling auto_select only changes the hardware register but doesn't update the cpufreq policy constraints, which can lead to inconsistent behavior between the hardware state and the policy limits visible to userspace and other kernel components. When auto_select is enabled, preserve the current min/max performance values to maintain user-configured limits. When disabled, the hardware operates in a default mode where the OS directly controls performance, so update the policy limits accordingly. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 65 ++++++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 9946adfeeee4..c888733ce5da 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -639,6 +639,26 @@ static int cppc_cpufreq_set_mperf_limit(struct cpufreq= _policy *policy, u64 val, #define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) \ cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, fals= e) =20 +static int cppc_cpufreq_update_autosel_val(struct cpufreq_policy *policy, = bool auto_sel) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + int ret; + + pr_debug("cpu%d, auto_sel curr:%u, new:%d\n", cpu, cpu_data->perf_caps.au= to_sel, auto_sel); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + ret =3D cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("Failed to set auto_sel=3D%d for CPU%d (%d)\n", auto_sel, cpu, r= et); + return ret; + } + cpu_data->perf_caps.auto_sel =3D auto_sel; + + return 0; +} + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; @@ -902,8 +922,47 @@ static ssize_t show_auto_select(struct cpufreq_policy = *policy, char *buf) return sysfs_emit(buf, "%d\n", val); } =20 -static ssize_t store_auto_select(struct cpufreq_policy *policy, - const char *buf, size_t count) +/** + * cppc_cpufreq_update_auto_select - Update autonomous selection config fo= r policy->cpu + * @policy: cpufreq policy + * @enable: enable/disable autonomous selection + */ +static int cppc_cpufreq_update_auto_select(struct cpufreq_policy *policy, = bool enable) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + u64 min_perf =3D caps->lowest_nonlinear_perf; + u64 max_perf =3D caps->nominal_perf; + int ret; + + if (enable) { + if (cpu_data->perf_ctrls.min_perf) + min_perf =3D cpu_data->perf_ctrls.min_perf; + if (cpu_data->perf_ctrls.max_perf) + max_perf =3D cpu_data->perf_ctrls.max_perf; + } + + /* + * Set min/max performance registers and update policy constraints. + * When enabling: update both registers and policy. + * When disabling: update policy only. + */ + ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, enable, true); + if (ret) + return ret; + + ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, enable, true); + if (ret) + return ret; + + ret =3D cppc_cpufreq_update_autosel_val(policy, enable); + if (ret) + return ret; + + return 0; +} + +static ssize_t store_auto_select(struct cpufreq_policy *policy, const char= *buf, size_t count) { bool val; int ret; @@ -912,7 +971,7 @@ static ssize_t store_auto_select(struct cpufreq_policy = *policy, if (ret) return ret; =20 - ret =3D cppc_set_auto_sel(policy->cpu, val); + ret =3D cppc_cpufreq_update_auto_select(policy, val); if (ret) return ret; =20 --=20 2.34.1