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Wed, 1 Oct 2025 08:01:52 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v3 4/8] ACPI: CPPC: add APIs and sysfs interface for min/max_perf Date: Wed, 1 Oct 2025 20:31:00 +0530 Message-ID: <20251001150104.1275188-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001150104.1275188-1-sumitg@nvidia.com> References: <20251001150104.1275188-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|CY5PR12MB6621:EE_ X-MS-Office365-Filtering-Correlation-Id: adc3413c-82c0-41a9-9e11-08de00fb8823 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 15:02:25.2055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adc3413c-82c0-41a9-9e11-08de00fb8823 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6621 Content-Type: text/plain; charset="utf-8" CPPC allows platforms to specify minimum and maximum performance limits that constrain the operating range for CPU performance scaling when Autonomous Selection is enabled. These limits can be dynamically adjusted to implement power management policies or workload-specific optimizations. Add cppc_get_min_perf() and cppc_set_min_perf() functions to read and write the MIN_PERF register, allowing dynamic adjustment of the minimum performance floor. Add cppc_get_max_perf() and cppc_set_max_perf() functions to read and write the MAX_PERF register, enabling dynamic ceiling control for maximum performance. Expose these capabilities through cpufreq sysfs attributes: - /sys/.../cpufreq/policy*/min_perf: Read/write min performance limit - /sys/.../cpufreq/policy*/max_perf: Read/write max performance limit Also update EPP constants for better clarity: - Rename CPPC_ENERGY_PERF_MAX to CPPC_EPP_ENERGY_EFFICIENCY_PREF - Add CPPC_EPP_PERFORMANCE_PREF for the performance-oriented setting Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 55 +++++++++++++++- drivers/cpufreq/cppc_cpufreq.c | 115 +++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 23 ++++++- 3 files changed, 191 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 12b2516b971c..d47aec2aed13 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1630,7 +1630,7 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); */ int cppc_set_epp(int cpu, u64 epp_val) { - if (epp_val > CPPC_ENERGY_PERF_MAX) + if (epp_val > CPPC_EPP_ENERGY_EFFICIENCY_PREF) return -EINVAL; =20 return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val); @@ -1753,6 +1753,59 @@ int cppc_set_enable(int cpu, bool enable) return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); + +/** + * cppc_get_min_perf - Get the min performance register value. + * @cpu: CPU from which to get min performance. + * @min_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return cppc_get_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_min_perf); + +/** + * cppc_set_min_perf() - Write the min performance register. + * @cpu: CPU on which to write register. + * @min_perf: Value to write to the MIN_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return cppc_set_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_min_perf); + +/** + * cppc_get_max_perf - Get the max performance register value. + * @cpu: CPU from which to get max performance. + * @max_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if = not supported. + */ +int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return cppc_get_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_max_perf); + +/** + * cppc_set_max_perf() - Write the max performance register. + * @cpu: CPU on which to write register. + * @max_perf: Value to write to the MAX_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return cppc_set_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_max_perf); + /** * cppc_get_perf - Get a CPU's performance controls. * @cpu: CPU for which to get performance controls. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 732f35096991..864978674efc 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -23,6 +23,7 @@ #include =20 #include +#include =20 #include =20 @@ -38,6 +39,8 @@ static enum { module_param(fie_disabled, int, 0444); MODULE_PARM_DESC(fie_disabled, "Disable Frequency Invariance Engine (FIE)"= ); =20 +static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); + /* Frequency invariance support */ struct cppc_freq_invariance { int cpu; @@ -572,6 +575,70 @@ static void cppc_cpufreq_put_cpu_data(struct cpufreq_p= olicy *policy) policy->driver_data =3D NULL; } =20 +/** + * cppc_cpufreq_set_mperf_limit - Generic function to set min/max performa= nce limit + * @policy: cpufreq policy + * @val: performance value to set + * @update_reg: whether to update hardware register + * @update_policy: whether to update policy constraints + * @is_min: true for min_perf, false for max_perf + */ +static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64= val, + bool update_reg, bool update_policy, bool is_min) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + unsigned int cpu =3D policy->cpu; + struct freq_qos_request *req; + unsigned int freq; + u32 perf; + int ret; + + perf =3D clamp(val, caps->lowest_perf, caps->highest_perf); + freq =3D cppc_perf_to_khz(caps, perf); + + pr_debug("cpu%d, %s_perf:%llu, update_reg:%d, update_policy:%d\n", cpu, + is_min ? "min" : "max", (u64)perf, update_reg, update_policy); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + if (update_reg) { + ret =3D is_min ? cppc_set_min_perf(cpu, perf) : cppc_set_max_perf(cpu, p= erf); + if (ret =3D=3D -EOPNOTSUPP) + return 0; + if (ret) { + pr_warn("Failed to set %s_perf (%llu) on CPU%d (%d)\n", + is_min ? "min" : "max", (u64)perf, cpu, ret); + return ret; + } + + /* Update cached value only on success */ + if (is_min) + cpu_data->perf_ctrls.min_perf =3D perf; + else + cpu_data->perf_ctrls.max_perf =3D perf; + } + + if (update_policy) { + req =3D is_min ? policy->min_freq_req : policy->max_freq_req; + + ret =3D freq_qos_update_request(req, freq); + if (ret < 0) { + pr_warn("Failed to update %s_freq constraint for CPU%d: %d\n", + is_min ? "min" : "max", cpu, ret); + return ret; + } + } + + return 0; +} + +#define cppc_cpufreq_set_min_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, true) + +#define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, fals= e) + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; @@ -873,16 +940,64 @@ static ssize_t store_energy_performance_preference_va= l(struct cpufreq_policy *po return cppc_cpufreq_sysfs_store_u64(buf, count, cppc_set_epp, policy->cpu= ); } =20 +static ssize_t show_min_perf(struct cpufreq_policy *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_min_perf, buf); +} + +static ssize_t store_min_perf(struct cpufreq_policy *policy, const char *b= uf, size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 val; + int ret; + + ret =3D kstrtou64(buf, 0, &val); + if (ret) + return ret; + + ret =3D cppc_cpufreq_set_min_perf(policy, val, true, cpu_data->perf_caps.= auto_sel); + if (ret) + return ret; + + return count; +} + +static ssize_t show_max_perf(struct cpufreq_policy *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_max_perf, buf); +} + +static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *b= uf, size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 val; + int ret; + + ret =3D kstrtou64(buf, 0, &val); + if (ret) + return ret; + + ret =3D cppc_cpufreq_set_max_perf(policy, val, true, cpu_data->perf_caps.= auto_sel); + if (ret) + return ret; + + return count; +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); +cpufreq_freq_attr_rw(min_perf); +cpufreq_freq_attr_rw(max_perf); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, &auto_select, &auto_act_window, &energy_performance_preference_val, + &min_perf, + &max_perf, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 3babc6d6e70a..fc7614eb9dcb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -39,7 +39,8 @@ /* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 w= hen writing */ #define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129 =20 -#define CPPC_ENERGY_PERF_MAX (0xFF) +#define CPPC_EPP_PERFORMANCE_PREF 0x00 +#define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF =20 /* Each register has the folowing format. */ struct cpc_reg { @@ -172,6 +173,10 @@ extern int cppc_get_auto_act_window(int cpu, u64 *auto= _act_window); extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); +extern int cppc_get_min_perf(int cpu, u64 *min_perf); +extern int cppc_set_min_perf(int cpu, u64 min_perf); +extern int cppc_get_max_perf(int cpu, u64 *max_perf); +extern int cppc_set_max_perf(int cpu, u64 max_perf); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -264,6 +269,22 @@ static inline int cppc_set_auto_sel(int cpu, bool enab= le) { return -EOPNOTSUPP; } +static inline int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1