From nobody Wed Oct 1 21:34:40 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD4D52EB852; Wed, 1 Oct 2025 12:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759321476; cv=none; b=rsp6lewNlPovCd0jVDpez1AFsBvm40DPsKXR8K29Cv5WKFOSIm4NbSdlcZe4vT78Jy5yfLknewwuUFJzxyt3oADQgrBKqR8QGFd4W92eU7XP/szOFl9UP2NNncZER1IEzza6ggKyq5L+RLO23mLEH7b1ly2y4JKhamADrJbZ/oU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759321476; c=relaxed/simple; bh=XQ3XKuMVVnlhB58MduVr+0rxBWpHh/TwGzeY/ypNSww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XukaiopPxSyvm1Gjtk9X1B6+eASQ5+tdEm/jo25urqcWpsp9tS7MCLnyAJCpat+4Nc4kvb/ZpvgmRsHINDvJD+pj1YoQiAL32eSj6z8ipLIgQMbn4rcRsPaekqWtOal02dIJGSyhj5Q15ZQ2dbtIPvKidvS9TVoq6GnVKtb0wA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: P0A2ztAXT0a/ptPrxWlU/g== X-CSE-MsgGUID: Tv38kF6gTAW37LXoCgsmNQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Oct 2025 21:24:34 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 53AA04197143; Wed, 1 Oct 2025 21:24:30 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/7] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs Date: Wed, 1 Oct 2025 15:23:13 +0300 Message-ID: <20251001122326.4024391-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251001122326.4024391-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251001122326.4024391-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ADCs on RZ/T2H and RZ/N2H are exposed on the evaluation kit boards. Enable them. Signed-off-by: Cosmin Tanislav --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 28 +++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 64 +++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 79 +++++++++++++++++++ 3 files changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 9170c563208a..e94b84393bd9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -252,3 +252,31 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 279f2510044b..d27da157c6d6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -305,3 +305,67 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; + + channel@6 { + reg =3D <0x6>; + }; + + channel@7 { + reg =3D <0x7>; + }; + + channel@8 { + reg =3D <0x8>; + }; + + channel@9 { + reg =3D <0x9>; + }; + + channel@a { + reg =3D <0xa>; + }; + + channel@b { + reg =3D <0xb>; + }; + + channel@c { + reg =3D <0xc>; + }; + + channel@d { + reg =3D <0xd>; + }; + + channel@e { + reg =3D <0xe>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 9ca26725a3e9..a7123a9ec684 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -338,3 +338,82 @@ &wdt2 { status =3D "okay"; timeout-sec =3D <60>; }; + +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] =3D ON, SW17[2] =3D OFF - Potentiometer + * SW17[1] =3D OFF, SW17[2] =3D ON - CN41 header + * N2H: + * DSW6[1] =3D OFF, DSW6[2] =3D ON - Potentiometer + * DSW6[1] =3D ON, DSW6[2] =3D OFF - CN3 header + */ +&adc0 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] =3D ON, SW18[2] =3D OFF - CN42 header + * SW18[1] =3D OFF, SW18[2] =3D ON - mikroBUS + * N2H: + * DSW6[3] =3D ON, DSW6[4] =3D OFF - CN4 header + * DSW6[3] =3D OFF, DSW6[4] =3D ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] =3D ON, SW18[4] =3D OFF - CN42 header + * SW18[3] =3D OFF, SW18[4] =3D ON - Grove2 + * N2H: + * DSW6[5] =3D ON, DSW6[6] =3D OFF - CN4 header + * DSW6[5] =3D OFF, DSW6[6] =3D ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] =3D ON, SW18[6] =3D OFF - CN42 header + * SW18[5] =3D OFF, SW18[6] =3D ON - Grove2 + * N2H: + * DSW6[7] =3D ON, DSW6[8] =3D OFF - CN4 header + * DSW6[7] =3D OFF, DSW6[8] =3D ON - Grove2 + */ +&adc1 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; --=20 2.51.0