From nobody Wed Oct 1 22:19:18 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB6EA2C236C; Wed, 1 Oct 2025 11:13:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759317208; cv=none; b=mNdyyArCDi1nFXzdTowwh8RAyhDVcf3ztKT1fP3TVikHn1lcXW9oJ/GdMDxopphwEMSazQSCLPgXATCoYWPefPoFG7h+G5vszbSIUWTrgz15XEfw4SnWfMIcRFfM6j41E/zs0dMk4/hAFopGLjGA01y7k8BI6gljQaXC96giy3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759317208; c=relaxed/simple; bh=HkFEltsRwVCksqBLmsRy4RMTYaoEdEQpTPcc8Ecnodw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aJegjMY5GrwcJYkXBGmhvgHklVm1z8G8+uPTlQLXVGtovHz1lCaMMnIAlD2KkkOyu69FV6e65v7JXsysLV1WZ1luiYfWB834mKoR30wVraqmaHLN/bX0LL4/ELxMHG8NQrlBL9LjEEIvACEiRLN6fFjTP90lcWgqUxw+gon3XHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=eIso9l8d; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="eIso9l8d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1759317205; bh=HkFEltsRwVCksqBLmsRy4RMTYaoEdEQpTPcc8Ecnodw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eIso9l8dVWGvYbimUbjpe3zRIfZUxZb0OqJxuuq3DyMmQ5j4NhR3THCnPbXW5Yba+ E0WPll64xvY0paWiSMGZdHyHh9QN8887dWvRHW83C72S5kdLLUO27pBsqqASAoeJTc qewj+yc7zS/xGGBHgCeTk6hfKz/TjkbNb6XXkC/PTDH1SkPtZJY9RQqYMrma30Zvw9 NV7gLQ5HmCaD1PZD2Fb/3sKMcbQArmEwUk18K6rMrGMBpxIYpk1HayszJcd+nCj1AE lsoHHYqnMb3jGJoEcXe9TvfTf425o8Nu6RRP3aI6WB5Jg2n7IJWb/eveWZfDXI0zUU 0wtOK9p3Lag5A== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 76AC017E131B; Wed, 1 Oct 2025 13:13:24 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, lgirdwood@gmail.com, broonie@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, igor.belwon@mentallysanemainliners.org Subject: [PATCH v6 3/9] dt-bindings: regulator: Document MediaTek MT6363 PMIC Regulators Date: Wed, 1 Oct 2025 13:13:10 +0200 Message-ID: <20251001111316.31828-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251001111316.31828-1-angelogioacchino.delregno@collabora.com> References: <20251001111316.31828-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for the regulators found in the MediaTek MT6363 PMIC, usually found in board designs using the MT6991 Dimensity 9400 and on MT8196 Kompanio SoC for Chromebooks, along with the MT6316 and MT6373 PMICs. Link: https://lore.kernel.org/r/20250715140224.206329-4-angelogioacchino.de= lregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) --- .../regulator/mediatek,mt6363-regulator.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt= 6363-regulator.yaml diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6363-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6363-= regulator.yaml new file mode 100644 index 000000000000..fe8ea3d04ae8 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6363-regulator= .yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6363-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6363 PMIC Regulators + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MT6363 SPMI PMIC provides 10 BUCK and 25 LDO (Low DropOut) regulators + and can optionally provide overcurrent warnings with one ocp interrupt + for each voltage regulator. + +properties: + compatible: + const: mediatek,mt6363-regulator + + reg: + maxItems: 1 + + vsys-vbuck1-supply: + description: Input supply for vbuck1 + + vsys-vbuck2-supply: + description: Input supply for vbuck2 + + vsys-vbuck3-supply: + description: Input supply for vbuck3 + + vsys-vbuck4-supply: + description: Input supply for vbuck4 + + vsys-vbuck5-supply: + description: Input supply for vbuck5 + + vsys-vbuck6-supply: + description: Input supply for vbuck6 + + vsys-vbuck7-supply: + description: Input supply for vbuck7 + + vsys-vs1-supply: + description: Input supply for vs1 + + vsys-vs2-supply: + description: Input supply for vs2 + + vsys-vs3-supply: + description: Input supply for vs3 + + vs1-ldo1-supply: + description: Input supply for va15, vio0p75, vm18, vrf18, vrf-io18 + + vs1-ldo2-supply: + description: Input supply for vcn15, vio18, vufs18 + + vs2-ldo1-supply: + description: Input supply for vsram-cpub, vsram-cpum, vrf12, vrf13, vu= fs12 + + vs2-ldo2-supply: + description: Input supply for va12-1, va12-2, vcn13, vsram-cpul + + vs3-ldo1-supply: + description: Input supply for vsram-apu, vsram-digrf, vsram-mdfe + + vs3-ldo2-supply: + description: Input supply for vsram-modem, vrf0p9 + + vsys-ldo1-supply: + description: Input supply for vaux18, vemc, vtref18 + +patternProperties: + "^v(buck[1-7]|s[1-3])$": + description: Buck regulators + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed Buck regulator operating modes allowed. Valid values bel= ow. + 0 - Normal mode with automatic power saving, reducing the swit= ching + frequency when light load conditions are detected + 1 - Forced Continuous Conduction mode (FCCM) for improved volt= age + regulation accuracy with constant switching frequency but = lower + regulator efficiency + 2 - Forced Low Power mode for improved regulator efficiency, u= sed + when no heavy load is expected, does not limit the maximum= out + current but unless only a light load is applied, there wil= l be + regulation accuracy and efficiency losses. + 3 - Forced Ultra Low Power mode for ultra low load, this great= ly + reduces the maximum output power, makes the regulator to be + efficient only for ultra light load, and greatly reduces t= he + quiescent current (Iq) of the buck. + maxItems: 3 + items: + enum: [ 0, 1, 2, 3 ] + + "^va(12-1|12-2|15)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^v(aux|m|rf-io|tref)18$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^v(cn13|cn15|emc)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^vio(0p75|18)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^vrf(0p9|12|13|18)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^vsram-(apu|cpub|cpum|cpul|digrf|mdfe|modem)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + + "^vufs(12|18)$": + $ref: "#/$defs/mediatek-mt6363-ldo-common" + +$defs: + mediatek-mt6363-ldo-common: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed LDO regulator operating modes allowed. Valid values belo= w. + 0 - Normal mode with automatic power saving, reducing the swit= ching + frequency when light load conditions are detected + 2 - Forced Low Power mode for improved regulator efficiency, u= sed + when no heavy load is expected, does not limit the maximum= out + current but unless only a light load is applied, there wil= l be + regulation accuracy and efficiency losses. + maxItems: 2 + items: + enum: [ 0, 2 ] + +required: + - compatible + - reg + +additionalProperties: false --=20 2.51.0