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charset="utf-8" From: Marc Kleine-Budde This is a preparation patch to add GPIO support. Up to now, the Vdd regulator and the clocks have been managed by Runtime-PM (on systems without CONFIG_PM these remain permanently switched on). During the mcp251xfd_open() callback the mcp251xfd is powered, soft-reset and configured. In mcp251xfd_stop() the chip is shut down again. To support the on-chip GPIOs, the chip must be supplied with power while GPIOs are being requested, even if the networking interface is down. To support this, move the functions mcp251xfd_chip_softreset() and mcp251xfd_chip_clock_init() from mcp251xfd_chip_start() to mcp251xfd_runtime_resume(). Instead of setting the controller to sleep mode in mcp251xfd_chip_stop(), bring it into configuration mode. This way it doesn't take part in bus activity and doesn't enter sleep mode. Signed-off-by: Marc Kleine-Budde Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 91 ++++++++++++------- 1 file changed, 57 insertions(+), 34 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index 7450ea42c1ea..f9eabb1810cf 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -767,21 +767,13 @@ static void mcp251xfd_chip_stop(struct mcp251xfd_priv= *priv, mcp251xfd_chip_interrupts_disable(priv); mcp251xfd_chip_rx_int_disable(priv); mcp251xfd_timestamp_stop(priv); - mcp251xfd_chip_sleep(priv); + mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); } =20 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) { int err; =20 - err =3D mcp251xfd_chip_softreset(priv); - if (err) - goto out_chip_stop; - - err =3D mcp251xfd_chip_clock_init(priv); - if (err) - goto out_chip_stop; - err =3D mcp251xfd_chip_timestamp_init(priv); if (err) goto out_chip_stop; @@ -1625,8 +1617,11 @@ static int mcp251xfd_open(struct net_device *ndev) return err; =20 err =3D pm_runtime_resume_and_get(ndev->dev.parent); - if (err) + if (err) { + if (err =3D=3D -ETIMEDOUT || err =3D=3D -ENODEV) + pm_runtime_set_suspended(ndev->dev.parent); goto out_close_candev; + } =20 err =3D mcp251xfd_ring_alloc(priv); if (err) @@ -1907,53 +1902,53 @@ static int mcp251xfd_register(struct mcp251xfd_priv= *priv) struct net_device *ndev =3D priv->ndev; int err; =20 + mcp251xfd_register_quirks(priv); + err =3D mcp251xfd_clks_and_vdd_enable(priv); if (err) return err; =20 - pm_runtime_get_noresume(ndev->dev.parent); - err =3D pm_runtime_set_active(ndev->dev.parent); - if (err) - goto out_runtime_put_noidle; - pm_runtime_enable(ndev->dev.parent); - - mcp251xfd_register_quirks(priv); - err =3D mcp251xfd_chip_softreset(priv); if (err =3D=3D -ENODEV) - goto out_runtime_disable; + goto out_clks_and_vdd_disable; if (err) goto out_chip_sleep; =20 err =3D mcp251xfd_chip_clock_init(priv); if (err =3D=3D -ENODEV) - goto out_runtime_disable; + goto out_clks_and_vdd_disable; if (err) goto out_chip_sleep; =20 + pm_runtime_get_noresume(ndev->dev.parent); + err =3D pm_runtime_set_active(ndev->dev.parent); + if (err) + goto out_runtime_put_noidle; + pm_runtime_enable(ndev->dev.parent); + err =3D mcp251xfd_register_chip_detect(priv); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 err =3D mcp251xfd_register_check_rx_int(priv); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 mcp251xfd_ethtool_init(priv); =20 err =3D register_candev(ndev); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 err =3D mcp251xfd_register_done(priv); if (err) goto out_unregister_candev; =20 - /* Put controller into sleep mode and let pm_runtime_put() - * disable the clocks and vdd. If CONFIG_PM is not enabled, - * the clocks and vdd will stay powered. + /* Put controller into Config mode and let pm_runtime_put() + * put in sleep mode, disable the clocks and vdd. If CONFIG_PM + * is not enabled, the clocks and vdd will stay powered. */ - err =3D mcp251xfd_chip_sleep(priv); + err =3D mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); if (err) goto out_unregister_candev; =20 @@ -1963,12 +1958,13 @@ static int mcp251xfd_register(struct mcp251xfd_priv= *priv) =20 out_unregister_candev: unregister_candev(ndev); -out_chip_sleep: - mcp251xfd_chip_sleep(priv); out_runtime_disable: pm_runtime_disable(ndev->dev.parent); out_runtime_put_noidle: pm_runtime_put_noidle(ndev->dev.parent); +out_chip_sleep: + mcp251xfd_chip_sleep(priv); +out_clks_and_vdd_disable: mcp251xfd_clks_and_vdd_disable(priv); =20 return err; @@ -1980,10 +1976,12 @@ static inline void mcp251xfd_unregister(struct mcp2= 51xfd_priv *priv) =20 unregister_candev(ndev); =20 - if (pm_runtime_enabled(ndev->dev.parent)) + if (pm_runtime_enabled(ndev->dev.parent)) { pm_runtime_disable(ndev->dev.parent); - else + } else { + mcp251xfd_chip_sleep(priv); mcp251xfd_clks_and_vdd_disable(priv); + } } =20 static const struct of_device_id mcp251xfd_of_match[] =3D { @@ -2206,16 +2204,41 @@ static void mcp251xfd_remove(struct spi_device *spi) =20 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) { - const struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); =20 + mcp251xfd_chip_sleep(priv); return mcp251xfd_clks_and_vdd_disable(priv); } =20 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) { - const struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + int err; + + err =3D mcp251xfd_clks_and_vdd_enable(priv); + if (err) + return err; =20 - return mcp251xfd_clks_and_vdd_enable(priv); + err =3D mcp251xfd_chip_softreset(priv); + if (err =3D=3D -ENODEV) + goto out_clks_and_vdd_disable; + if (err) + goto out_chip_sleep; + + err =3D mcp251xfd_chip_clock_init(priv); + if (err =3D=3D -ENODEV) + goto out_clks_and_vdd_disable; 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charset="utf-8" From: Gregor Herburger This is a preparation patch to add errata workaround for non crc writes. Currently for non-crc writes to the chip can go through the .gather_write, .write or the reg_update_bits callback. To allow the addition of the errata fix at a single location use mcp251xfd_regmap_nocrc_gather_write for all non-CRC write instructions, similar to the crc regmap. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 25 ++++++++++--------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index 8c5be8d1c519..e61cbd209955 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -12,14 +12,6 @@ =20 static const struct regmap_config mcp251xfd_regmap_crc; =20 -static int -mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) -{ - struct spi_device *spi =3D context; - - return spi_write(spi, data, count); -} - static int mcp251xfd_regmap_nocrc_gather_write(void *context, const void *reg, size_t reg_len, @@ -47,6 +39,15 @@ mcp251xfd_regmap_nocrc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) +{ + const size_t data_offset =3D sizeof(__be16); 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charset="utf-8" From: Gregor Herburger According to Errata DS80000789E 5 writing IOCON register using one SPI write command clears LAT0/LAT1. Errata Fix/Work Around suggests to write registers with single byte write instructions. However, it seems that every write to the second byte causes the overwrite of LAT0/LAT1. Never write byte 2 of IOCON register to avoid clearing of LAT0/LAT1. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 89 +++++++++++++++++-- 1 file changed, 83 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index e61cbd209955..70d5ff0ae7ac 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -13,9 +13,9 @@ static const struct regmap_config mcp251xfd_regmap_crc; =20 static int -mcp251xfd_regmap_nocrc_gather_write(void *context, - const void *reg, size_t reg_len, - const void *val, size_t val_len) +_mcp251xfd_regmap_nocrc_gather_write(void *context, + const void *reg, size_t reg_len, + const void *val, size_t val_len) { struct spi_device *spi =3D context; struct mcp251xfd_priv *priv =3D spi_get_drvdata(spi); @@ -39,6 +39,45 @@ mcp251xfd_regmap_nocrc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_nocrc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) +{ + const u16 byte_exclude =3D MCP251XFD_REG_IOCON + + mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK); + u16 reg =3D be16_to_cpu(*(__be16 *)reg_p) & MCP251XFD_SPI_ADDRESS_MASK; + int ret; + + /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0= /LAT1 + * + * According to MCP2518FD Errata DS80000789E 5 writing IOCON register usi= ng one + * SPI write command clears LAT0/LAT1. + * + * Errata Fix/Work Around suggests to write registers with single byte + * write instructions. However, it seems that the byte at 0xe06(IOCON[23:= 16]) + * is for read-only access and writing to it causes the clearing of LAT0/= LAT1. + */ + if (reg <=3D byte_exclude && reg + val_len > byte_exclude) { + size_t len =3D byte_exclude - reg; + + /* Write up to 0xe05 */ + ret =3D _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len, va= l, len); + if (ret) + return ret; + + /* Write from 0xe07 on */ + reg +=3D len + 1; + reg =3D (__force unsigned short)cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WR= ITE | reg); + return _mcp251xfd_regmap_nocrc_gather_write(context, ®, reg_len, + val + len + 1, + val_len - len - 1); + } + + return _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len, + val, val_len); +} + static int mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) { @@ -197,9 +236,9 @@ mcp251xfd_regmap_nocrc_read(void *context, } =20 static int -mcp251xfd_regmap_crc_gather_write(void *context, - const void *reg_p, size_t reg_len, - const void *val, size_t val_len) +_mcp251xfd_regmap_crc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) { struct spi_device *spi =3D context; struct mcp251xfd_priv *priv =3D spi_get_drvdata(spi); @@ -230,6 +269,44 @@ mcp251xfd_regmap_crc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_crc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) +{ + const u16 byte_exclude =3D MCP251XFD_REG_IOCON + + mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK); + u16 reg =3D *(u16 *)reg_p; + int ret; + + /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0= /LAT1 + * + * According to MCP2518FD Errata DS80000789E 5 writing IOCON register usi= ng one + * SPI write command clears LAT0/LAT1. + * + * Errata Fix/Work Around suggests to write registers with single byte + * write instructions. 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charset="utf-8" From: Gregor Herburger When rx_int is used th mcp251xfd_chip_rx_int_enable and mcp251xfd_chip_rx_int_disable function configure both PIN0 and PIN1. To prepare the support of the GPIOS only configure PIN1 with regmap_update_bits. This way PIN0 can be used as GPIO while PIN1 is used as rx_int interrupt. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 22 +++++++------------ drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 6 +++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index f9eabb1810cf..ea41f04ae1a6 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -608,23 +608,21 @@ static int mcp251xfd_set_bittiming(const struct mcp25= 1xfd_priv *priv) =20 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) { - u32 val; + u32 val, mask; =20 if (!priv->rx_int) return 0; =20 - /* Configure GPIOs: - * - PIN0: GPIO Input - * - PIN1: GPIO Input/RX Interrupt + /* Configure PIN1 as RX Interrupt: * * PIN1 must be Input, otherwise there is a glitch on the * rx-INT line. It happens between setting the PIN as output * (in the first byte of the SPI transfer) and configuring the * PIN as interrupt (in the last byte of the SPI transfer). */ - val =3D MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | - MCP251XFD_REG_IOCON_TRIS0; - return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); + val =3D MCP251XFD_REG_IOCON_TRIS(1); + mask =3D MCP251XFD_REG_IOCON_TRIS(1) | MCP251XFD_REG_IOCON_PM(1); + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, mask, val); } =20 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) @@ -634,13 +632,9 @@ static int mcp251xfd_chip_rx_int_disable(const struct = mcp251xfd_priv *priv) if (!priv->rx_int) return 0; =20 - /* Configure GPIOs: - * - PIN0: GPIO Input - * - PIN1: GPIO Input - */ - val =3D MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | - MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; - return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); + /* Configure PIN1 as GPIO Input */ + val =3D MCP251XFD_REG_IOCON_PM(1) | MCP251XFD_REG_IOCON_TRIS(1); + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, val, val); } =20 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/sp= i/mcp251xfd/mcp251xfd.h index dcbbd2b2fae8..bd28510a6583 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -335,13 +335,19 @@ #define MCP251XFD_REG_IOCON_TXCANOD BIT(28) #define MCP251XFD_REG_IOCON_PM1 BIT(25) #define MCP251XFD_REG_IOCON_PM0 BIT(24) +#define MCP251XFD_REG_IOCON_PM(n) (MCP251XFD_REG_IOCON_PM0 << (n)) #define MCP251XFD_REG_IOCON_GPIO1 BIT(17) #define MCP251XFD_REG_IOCON_GPIO0 BIT(16) +#define MCP251XFD_REG_IOCON_GPIO(n) (MCP251XFD_REG_IOCON_GPIO0 << (n)) +#define MCP251XFD_REG_IOCON_GPIO_MASK GENMASK(17, 16) #define MCP251XFD_REG_IOCON_LAT1 BIT(9) #define MCP251XFD_REG_IOCON_LAT0 BIT(8) +#define MCP251XFD_REG_IOCON_LAT(n) (MCP251XFD_REG_IOCON_LAT0 << (n)) +#define MCP251XFD_REG_IOCON_LAT_MASK GENMASK(9, 8) #define MCP251XFD_REG_IOCON_XSTBYEN BIT(6) #define MCP251XFD_REG_IOCON_TRIS1 BIT(1) #define MCP251XFD_REG_IOCON_TRIS0 BIT(0) +#define MCP251XFD_REG_IOCON_TRIS(n) (MCP251XFD_REG_IOCON_TRIS0 << (n)) =20 #define MCP251XFD_REG_CRC 0xe08 #define MCP251XFD_REG_CRC_FERRIE BIT(25) --=20 2.34.1 From nobody Wed Oct 1 21:24:17 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45BE2D9499 for ; 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charset="utf-8" From: Gregor Herburger The mcp251xfd devices allow two pins to be configured as gpio. Add this functionality to driver. Acked-by: Bartosz Golaszewski Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- drivers/net/can/spi/mcp251xfd/Kconfig | 1 + .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 160 ++++++++++++++++++ drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 2 + 3 files changed, 163 insertions(+) diff --git a/drivers/net/can/spi/mcp251xfd/Kconfig b/drivers/net/can/spi/mc= p251xfd/Kconfig index 877e4356010d..7c29846e6051 100644 --- a/drivers/net/can/spi/mcp251xfd/Kconfig +++ b/drivers/net/can/spi/mcp251xfd/Kconfig @@ -5,6 +5,7 @@ config CAN_MCP251XFD select CAN_RX_OFFLOAD select REGMAP select WANT_DEV_COREDUMP + select GPIOLIB help Driver for the Microchip MCP251XFD SPI FD-CAN controller family. diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index ea41f04ae1a6..586336d9e421 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -1797,6 +1797,160 @@ static int mcp251xfd_register_check_rx_int(struct m= cp251xfd_priv *priv) return 0; } =20 +static const char * const mcp251xfd_gpio_names[] =3D { "GPIO0", "GPIO1" }; + +static int mcp251xfd_gpio_request(struct gpio_chip *chip, unsigned int off= set) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 pin_mask =3D MCP251XFD_REG_IOCON_PM(offset); + int ret; + + if (priv->rx_int && offset =3D=3D 1) { + netdev_err(priv->ndev, "Can't use GPIO 1 with RX-INT!\n"); + return -EINVAL; + } + + ret =3D pm_runtime_resume_and_get(priv->ndev->dev.parent); + if (ret) + return ret; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, pin_mask, p= in_mask); +} + +static void mcp251xfd_gpio_free(struct gpio_chip *chip, unsigned int offse= t) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + + pm_runtime_put(priv->ndev->dev.parent); +} + +static int mcp251xfd_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + if (mask & val) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int mcp251xfd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_GPIO(offset); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + return !!(mask & val); +} + +static int mcp251xfd_gpio_get_multiple(struct gpio_chip *chip, unsigned lo= ng *mask, + unsigned long *bit) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + *bit =3D FIELD_GET(MCP251XFD_REG_IOCON_GPIO_MASK, val) & *mask; + + return 0; +} + +static int mcp251xfd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT(offset); + u32 val; + + if (value) + val =3D val_mask; + else + val =3D 0; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + dir_mask | val_mask, val); +} + +static int mcp251xfd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, dir_mask, d= ir_mask); +} + +static int mcp251xfd_gpio_set(struct gpio_chip *chip, unsigned int offset,= int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT(offset); + u32 val; + + if (value) + val =3D val_mask; + else + val =3D 0; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, val_mask, v= al); +} + +static int mcp251xfd_gpio_set_multiple(struct gpio_chip *chip, unsigned lo= ng *mask, + unsigned long *bits) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val; + + val =3D FIELD_PREP(MCP251XFD_REG_IOCON_LAT_MASK, *bits); + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + MCP251XFD_REG_IOCON_LAT_MASK, val); +} + +static int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv) +{ + struct gpio_chip *gc =3D &priv->gc; + + if (!device_property_present(&priv->spi->dev, "gpio-controller")) + return 0; + + gc->label =3D dev_name(&priv->spi->dev); + gc->parent =3D &priv->spi->dev; + gc->owner =3D THIS_MODULE; + gc->request =3D mcp251xfd_gpio_request; + gc->free =3D mcp251xfd_gpio_free; + gc->get_direction =3D mcp251xfd_gpio_get_direction; + gc->direction_output =3D mcp251xfd_gpio_direction_output; + gc->direction_input =3D mcp251xfd_gpio_direction_input; + gc->get =3D mcp251xfd_gpio_get; + gc->get_multiple =3D mcp251xfd_gpio_get_multiple; + gc->set =3D mcp251xfd_gpio_set; + gc->set_multiple =3D mcp251xfd_gpio_set_multiple; + gc->base =3D -1; + gc->can_sleep =3D true; + gc->ngpio =3D ARRAY_SIZE(mcp251xfd_gpio_names); + gc->names =3D mcp251xfd_gpio_names; + + return devm_gpiochip_add_data(&priv->spi->dev, gc, priv); +} + static int mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_= id, u32 *effective_speed_hz_slow, @@ -1930,6 +2084,12 @@ static int mcp251xfd_register(struct mcp251xfd_priv = *priv) =20 mcp251xfd_ethtool_init(priv); =20 + err =3D mcp251fdx_gpio_setup(priv); + if (err) { + dev_err_probe(&priv->spi->dev, err, "Failed to register gpio-controller.= \n"); + goto out_runtime_disable; + } + err =3D register_candev(ndev); if (err) goto out_runtime_disable; diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/sp= i/mcp251xfd/mcp251xfd.h index bd28510a6583..085d7101e595 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -676,6 +677,7 @@ struct mcp251xfd_priv { =20 struct mcp251xfd_devtype_data devtype_data; struct can_berr_counter bec; + struct gpio_chip gc; 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charset="utf-8" From: Gregor Herburger The mcp251xfd has two pins that can be used as gpio. Add gpio-controller property to binding description. Acked-by: Krzysztof Kozlowski Signed-off-by: Gregor Herburger Signed-off-by: Viken Dadhaniya --- .../devicetree/bindings/net/can/microchip,mcp251xfd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.= yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index c155c9c6db39..2d13638ebc6a 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -49,6 +49,11 @@ properties: Must be half or less of "clocks" frequency. maximum: 20000000 =20 + gpio-controller: true + + "#gpio-cells": + const: 2 + required: - compatible - reg --=20 2.34.1