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charset="utf-8" Add 'reg' and 'clocks' properties to enable QoS configuration. These properties enable access to QoS registers and necessary clocks for configuration. QoS configuration is essential for ensuring that latency sensitive components such as CPUs and multimedia engines receive prioritized access to memory and interconnect resources. This helps to manage bandwidth and latency across subsystems, improving system responsiveness and performance in concurrent workloads. Both 'reg' and 'clocks' properties are optional. If either is missing, QoS configuration will be skipped. This behavior is controlled by the 'qos_requires_clocks' flag in the driver, which ensures that QoS configuration is bypassed when required clocks are not defined. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,sa8775p-rpmh.yaml | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rp= mh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.= yaml index db19fd5c5708..71428d2cce18 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -33,18 +33,66 @@ properties: - qcom,sa8775p-pcie-anoc - qcom,sa8775p-system-noc =20 + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 5 + required: - compatible =20 allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre UFS CARD AXI clock + - description: RPMH CC IPA clock =20 unevaluatedProperties: false =20 examples: - | - aggre1_noc: interconnect-aggre1-noc { + #include + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sa8775p-clk-virt"; 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charset="utf-8" Enable QoS configuration for master ports with predefinedi priority and urgency forwarding. Signed-off-by: Odelu Kukatla --- drivers/interconnect/qcom/sa8775p.c | 439 ++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index 04b4abbf4487..5bf27dbe818d 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -213,6 +213,13 @@ static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -221,6 +228,13 @@ static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -229,6 +243,13 @@ static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -237,6 +258,13 @@ static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -245,6 +273,13 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -253,6 +288,13 @@ static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -261,6 +303,13 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -269,6 +318,13 @@ static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -277,6 +333,13 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -285,6 +348,13 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -293,6 +363,13 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -301,6 +378,13 @@ static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -309,6 +393,13 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -317,6 +408,13 @@ static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -325,6 +423,13 @@ static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -333,6 +438,13 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -341,6 +453,13 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -349,6 +468,13 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -357,6 +483,13 @@ static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -461,6 +594,13 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb4000 }, + .prio_fwd_disable =3D 1, + .prio =3D 1, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -469,6 +609,13 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb5000 }, + .prio_fwd_disable =3D 1, + .prio =3D 3, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -477,6 +624,13 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb6000 }, + .prio_fwd_disable =3D 1, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -494,6 +648,13 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf3000, 0xf4000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -502,6 +663,13 @@ static struct qcom_icc_node qnm_cmpnoc1 =3D { .name =3D "qnm_cmpnoc1", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf5000, 0xf6000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -527,6 +695,13 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xed000, 0xee000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -535,6 +710,13 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xef000, 0xf0000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, }; @@ -543,6 +725,13 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf1000, 0xf2000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -552,6 +741,13 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb8000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -560,6 +756,13 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb9000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, }; @@ -568,6 +771,13 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xba000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -620,6 +830,13 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -628,6 +845,13 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -636,6 +860,13 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -644,6 +875,13 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -652,6 +890,13 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -660,6 +905,13 @@ static struct qcom_icc_node qnm_mdp1_0 =3D { .name =3D "qnm_mdp1_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -668,6 +920,13 @@ static struct qcom_icc_node qnm_mdp1_1 =3D { .name =3D "qnm_mdp1_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -692,6 +951,13 @@ static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -700,6 +966,13 @@ static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -708,6 +981,13 @@ static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -716,6 +996,13 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a280 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -756,6 +1043,13 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -764,6 +1058,13 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -772,6 +1073,13 @@ static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -796,6 +1104,13 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -812,6 +1127,13 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -820,6 +1142,13 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -1836,12 +2165,22 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 +static const struct regmap_config sa8775p_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x18080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_aggre1_noc =3D { + .config =3D &sa8775p_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1864,12 +2203,22 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 +static const struct regmap_config sa8775p_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1b080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_aggre2_noc =3D { + .config =3D &sa8775p_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1995,7 +2344,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config sa8775p_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_config_noc =3D { + .config =3D &sa8775p_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -2012,7 +2370,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, }; =20 +static const struct regmap_config sa8775p_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_dc_noc =3D { + .config =3D &sa8775p_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -2049,7 +2416,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC2] =3D &srvc_sys_gemnoc_2, }; =20 +static const struct regmap_config sa8775p_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf6080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_gem_noc =3D { + .config =3D &sa8775p_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2068,7 +2444,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes= [] =3D { [SLAVE_GP_DSP_SAIL_NOC] =3D &qns_gp_dsp_sail_noc, }; =20 +static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_gpdsp_anoc =3D { + .config =3D &sa8775p_gpdsp_anoc_regmap_config, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -2092,7 +2477,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, }; =20 +static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_lpass_ag_noc =3D { + .config =3D &sa8775p_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2143,7 +2537,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, }; =20 +static const struct regmap_config sa8775p_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x40000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_mmss_noc =3D { + .config =3D &sa8775p_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2164,7 +2567,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[]= =3D { [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, }; =20 +static const struct regmap_config sa8775p_nspa_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_nspa_noc =3D { + .config =3D &sa8775p_nspa_noc_regmap_config, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -2177,6 +2589,14 @@ static struct qcom_icc_bcm * const nspb_noc_bcms[] = =3D { &bcm_nsb1, }; =20 +static const struct regmap_config sa8775p_nspb_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static struct qcom_icc_node * const nspb_noc_nodes[] =3D { [MASTER_CDSPB_NOC_CFG] =3D &qhm_nspb_noc_config, [MASTER_CDSP_PROC_B] =3D &qxm_nspb, @@ -2186,6 +2606,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sa8775p_nspb_noc =3D { + .config =3D &sa8775p_nspb_noc_regmap_config, .nodes =3D nspb_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, @@ -2203,7 +2624,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[= ] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 +static const struct regmap_config sa8775p_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_pcie_anoc =3D { + .config =3D &sa8775p_pcie_anoc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -2232,7 +2662,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, }; 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charset="utf-8" Add register addresses and clocks which need to be enabled for configuring QoS on sa8775p SoC. Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/lemans.dtsi | 163 +++++++++++++++------------ 1 file changed, 91 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index cf685cb186ed..3a02a515af0d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -518,90 +518,18 @@ }; }; =20 - aggre1_noc: interconnect-aggre1-noc { - compatible =3D "qcom,sa8775p-aggre1-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible =3D "qcom,sa8775p-aggre2-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible =3D "qcom,sa8775p-clk-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - config_noc: interconnect-config-noc { - compatible =3D "qcom,sa8775p-config-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible =3D "qcom,sa8775p-dc-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible =3D "qcom,sa8775p-gem-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gpdsp_anoc: interconnect-gpdsp-anoc { - compatible =3D "qcom,sa8775p-gpdsp-anoc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect-lpass-ag-noc { - compatible =3D "qcom,sa8775p-lpass-ag-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible =3D "qcom,sa8775p-mc-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - mmss_noc: interconnect-mmss-noc { - compatible =3D "qcom,sa8775p-mmss-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible =3D "qcom,sa8775p-nspa-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible =3D "qcom,sa8775p-nspb-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - pcie_anoc: interconnect-pcie-anoc { - compatible =3D "qcom,sa8775p-pcie-anoc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible =3D "qcom,sa8775p-system-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - /* Will be updated by the bootloader. */ memory@80000000 { device_type =3D "memory"; @@ -2689,6 +2617,62 @@ reg =3D <0 0x010d2000 0 0x1000>; }; =20 + config_noc: interconnect@14c0000 { + compatible =3D "qcom,sa8775p-config-noc"; + reg =3D <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sa8775p-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,sa8775p-aggre1-noc"; + reg =3D <0x0 0x016c0000 0x0 0x18080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sa8775p-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1b080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + pcie_anoc: interconnect@1760000 { + compatible =3D "qcom,sa8775p-pcie-anoc"; + reg =3D <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible =3D "qcom,sa8775p-gpdsp-anoc"; + reg =3D <0x0 0x01780000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible =3D "qcom,sa8775p-mmss-noc"; + reg =3D <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; @@ -2769,6 +2753,13 @@ <&apps_smmu 0x481 0x00>; }; =20 + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,sa8775p-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + ctcu@4001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x0 0x04001000 0x0 0x1000>; @@ -3925,6 +3916,20 @@ status =3D "disabled"; }; =20 + dc_noc: interconnect@90e0000 { + compatible =3D "qcom,sa8775p-dc-noc"; + reg =3D <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible =3D "qcom,sa8775p-gem-noc"; + reg =3D <0x0 0x09100000 0x0 0xf6080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + usb_0: usb@a600000 { compatible =3D "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg =3D <0 0x0a600000 0 0xfc100>; @@ -6875,6 +6880,13 @@ status =3D "disabled"; }; =20 + nspa_noc: interconnect@260c0000 { + compatible =3D "qcom,sa8775p-nspa-noc"; + reg =3D <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_cdsp0: remoteproc@26300000 { compatible =3D "qcom,sa8775p-cdsp0-pas"; reg =3D <0x0 0x26300000 0x0 0x10000>; @@ -7007,6 +7019,13 @@ }; }; =20 + nspb_noc: interconnect@2a0c0000 { + compatible =3D "qcom,sa8775p-nspb-noc"; + reg =3D <0x0 0x2a0c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_cdsp1: remoteproc@2a300000 { compatible =3D "qcom,sa8775p-cdsp1-pas"; reg =3D <0x0 0x2A300000 0x0 0x10000>; --=20 2.17.1