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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:53.8576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d9f4cd6-ff57-41c3-e4f9-08de00b14756 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4043 Content-Type: text/plain; charset="utf-8" To allow reuse in other files in subsequent patches Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c7cb4a80d44a..d533bb8851ea 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -187,6 +187,7 @@ void amd_iommu_domain_set_pgtable(struct protection_dom= ain *domain, u64 *root, int mode); struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); +int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 /* DTE */ int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 386ac96b2c02..e0bfcda678a8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1392,7 +1392,7 @@ static int iommu_queue_command(struct amd_iommu *iomm= u, struct iommu_cmd *cmd) * This function queues a completion wait command into the command * buffer of an IOMMU */ -static int iommu_completion_wait(struct amd_iommu *iommu) +int amd_iommu_completion_wait(struct amd_iommu *iommu) { struct iommu_cmd cmd; unsigned long flags; @@ -1431,7 +1431,7 @@ static void domain_flush_complete(struct protection_d= omain *domain) * We need to wait for completion of all commands. */ xa_for_each(&domain->iommu_array, i, pdom_iommu_info) - iommu_completion_wait(pdom_iommu_info->iommu); + amd_iommu_completion_wait(pdom_iommu_info->iommu); } =20 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) @@ -1449,7 +1449,7 @@ static void iommu_flush_dte_sync(struct amd_iommu *io= mmu, u16 devid) =20 ret =3D iommu_flush_dte(iommu, devid); if (!ret) - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) @@ -1460,7 +1460,7 @@ static void amd_iommu_flush_dte_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; ++devid) iommu_flush_dte(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 /* @@ -1479,7 +1479,7 @@ static void amd_iommu_flush_tlb_all(struct amd_iommu = *iommu) iommu_queue_command(iommu, &cmd); } =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) @@ -1490,7 +1490,7 @@ static void amd_iommu_flush_tlb_domid(struct amd_iomm= u *iommu, u32 dom_id) dom_id, IOMMU_NO_PASID, false); iommu_queue_command(iommu, &cmd); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_all(struct amd_iommu *iommu) @@ -1500,7 +1500,7 @@ static void amd_iommu_flush_all(struct amd_iommu *iom= mu) build_inv_all(&cmd); =20 iommu_queue_command(iommu, &cmd); - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) @@ -1523,7 +1523,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; devid++) iommu_flush_irt(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 void amd_iommu_flush_all_caches(struct amd_iommu *iommu) @@ -1748,7 +1748,7 @@ void amd_iommu_dev_flush_pasid_pages(struct iommu_dev= _data *dev_data, if (dev_data->ats_enabled) device_flush_iotlb(dev_data, address, size, pasid, true); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void dev_flush_pasid_all(struct iommu_dev_data *dev_data, @@ -2137,7 +2137,7 @@ static void dev_update_dte(struct iommu_dev_data *dev= _data, bool set) =20 clone_aliases(iommu, dev_data->dev); amd_iommu_device_flush_dte(dev_data); - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 /* @@ -2421,7 +2421,7 @@ static struct iommu_device *amd_iommu_probe_device(st= ruct device *dev) =20 out_err: =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); =20 if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; @@ -3255,7 +3255,7 @@ static struct irq_remap_table *alloc_irq_table(struct= amd_iommu *iommu, set_remap_table_entry(iommu, alias, table); =20 out_wait: - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); =20 out_unlock: spin_unlock_irqrestore(&iommu_table_lock, flags); --=20 2.34.1