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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:47.9323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b8a04b7-8fa9-45bc-cbdd-08de00b143cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5656 Content-Type: text/plain; charset="utf-8" To allow reuse in other files in subsequent patches. Also, remove unused function parameter ptr. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 7 +++++++ drivers/iommu/amd/iommu.c | 13 ++----------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index eb46e8914eaf..c7cb4a80d44a 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -193,5 +193,12 @@ int amd_iommu_device_flush_dte(struct iommu_dev_data *= dev_data); void amd_iommu_update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, struct dev_table_entry *new); +static inline void +amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table= _entry *new) +{ + /* All existing DTE must have V bit set */ + new->data128[0] =3D DTE_FLAG_V; + new->data128[1] =3D 0; +} =20 #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 3f2c61509b60..386ac96b2c02 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2008,14 +2008,6 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_= data, ioasid_t pasid) return ret; } =20 -static void make_clear_dte(struct iommu_dev_data *dev_data, struct dev_tab= le_entry *ptr, - struct dev_table_entry *new) -{ - /* All existing DTE must have V bit set */ - new->data128[0] =3D DTE_FLAG_V; - new->data128[1] =3D 0; -} - /* * Note: * The old value for GCR3 table and GPT have been cleared from caller. @@ -2068,7 +2060,7 @@ static void set_dte_entry(struct amd_iommu *iommu, else domid =3D domain->id; =20 - make_clear_dte(dev_data, dte, &new); + amd_iommu_make_clear_dte(dev_data, &new); =20 if (domain->iop.mode !=3D PAGE_MODE_NONE) new.data[0] |=3D iommu_virt_to_phys(domain->iop.root); @@ -2128,9 +2120,8 @@ static void set_dte_entry(struct amd_iommu *iommu, static void clear_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data= *dev_data) { struct dev_table_entry new =3D {}; - struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; =20 - make_clear_dte(dev_data, dte, &new); + amd_iommu_make_clear_dte(dev_data, &new); amd_iommu_update_dte256(iommu, dev_data, &new); } =20 --=20 2.34.1