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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:19.8022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28e5b334-ce3f-4cbe-2524-08de00b13309 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8288 Content-Type: text/plain; charset="utf-8" Also change the define to use GENMASK_ULL instead. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 2 +- drivers/iommu/amd/iommu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index a698a2e7ce2a..556f1df32d53 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -422,7 +422,7 @@ =20 #define DTE_FLAG_IOTLB BIT_ULL(32) #define DTE_FLAG_MASK (0x3ffULL << 32) -#define DEV_DOMID_MASK 0xffffULL +#define DTE_DOMID_MASK GENMASK_ULL(15, 0) =20 #define DTE_GCR3_14_12 GENMASK_ULL(60, 58) #define DTE_GCR3_30_15 GENMASK_ULL(31, 16) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b57a6993179d..a9b17d31a969 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2094,7 +2094,7 @@ static void set_dte_entry(struct amd_iommu *iommu, if (dev_data->ats_enabled) new.data[1] |=3D DTE_FLAG_IOTLB; =20 - old_domid =3D READ_ONCE(dte->data[1]) & DEV_DOMID_MASK; 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Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 9b4b589a54b5..6ea549816a1f 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -26,6 +26,7 @@ void amd_iommu_set_rlookup_table(struct amd_iommu *iommu,= u16 devid); void iommu_feature_enable(struct amd_iommu *iommu, u8 bit); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); +int amd_iommu_pdom_id_alloc(void); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS void amd_iommu_debugfs_setup(void); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a9b17d31a969..78b3e5485006 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1818,7 +1818,7 @@ int amd_iommu_complete_ppr(struct device *dev, u32 pa= sid, int status, int tag) * *************************************************************************= ***/ =20 -static int pdom_id_alloc(void) +int amd_iommu_pdom_id_alloc(void) { return ida_alloc_range(&pdom_ids, 1, MAX_DOMAIN_ID - 1, GFP_ATOMIC); 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Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 6ea549816a1f..322c8c73444a 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -27,6 +27,7 @@ void iommu_feature_enable(struct amd_iommu *iommu, u8 bit= ); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); int amd_iommu_pdom_id_alloc(void); +void amd_iommu_pdom_id_free(int id); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS void amd_iommu_debugfs_setup(void); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 78b3e5485006..0b61059e485d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1823,7 +1823,7 @@ int amd_iommu_pdom_id_alloc(void) return ida_alloc_range(&pdom_ids, 1, MAX_DOMAIN_ID - 1, GFP_ATOMIC); } =20 -static void pdom_id_free(int id) +void amd_iommu_pdom_id_free(int id) { ida_free(&pdom_ids, id); } @@ -1870,7 +1870,7 @@ static void free_gcr3_table(struct gcr3_tbl_info *gcr= 3_info) gcr3_info->glx =3D 0; =20 /* Free per device domain ID */ - pdom_id_free(gcr3_info->domid); + amd_iommu_pdom_id_free(gcr3_info->domid); =20 iommu_free_pages(gcr3_info->gcr3_tbl); gcr3_info->gcr3_tbl =3D NULL; @@ -1913,7 +1913,7 @@ static int setup_gcr3_table(struct gcr3_tbl_info *gcr= 3_info, =20 gcr3_info->gcr3_tbl =3D iommu_alloc_pages_node_sz(nid, GFP_ATOMIC, SZ_4K); if (gcr3_info->gcr3_tbl =3D=3D NULL) { - pdom_id_free(domid); + amd_iommu_pdom_id_free(domid); return -ENOMEM; } =20 @@ -2573,7 +2573,7 @@ do_iommu_domain_alloc(struct device *dev, u32 flags, domain->pd_mode =3D pgtable; ret =3D pdom_setup_pgtable(domain, dev); if (ret) { - pdom_id_free(domain->id); + amd_iommu_pdom_id_free(domain->id); kfree(domain); return ERR_PTR(ret); } @@ -2631,7 +2631,7 @@ void amd_iommu_domain_free(struct iommu_domain *dom) WARN_ON(!list_empty(&domain->dev_list)); if (domain->domain.type & __IOMMU_DOMAIN_PAGING) free_io_pgtable_ops(&domain->iop.pgtbl.ops); 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Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 3 +++ drivers/iommu/amd/iommu.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 322c8c73444a..079fb1d44c00 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -188,4 +188,7 @@ void amd_iommu_domain_set_pgtable(struct protection_dom= ain *domain, struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); =20 +/* DTE */ +int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); + #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 0b61059e485d..fad74d2bc1b1 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1562,7 +1562,7 @@ static int device_flush_dte_alias(struct pci_dev *pde= v, u16 alias, void *data) /* * Command send function for invalidating a device table entry */ -static int device_flush_dte(struct iommu_dev_data *dev_data) +int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data) { struct amd_iommu *iommu =3D get_amd_iommu_from_dev_data(dev_data); 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Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 3 +++ drivers/iommu/amd/iommu.c | 11 ++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 079fb1d44c00..eb46e8914eaf 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -190,5 +190,8 @@ struct iommu_dev_data *search_dev_data(struct amd_iommu= *iommu, u16 devid); =20 /* DTE */ int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); +void amd_iommu_update_dte256(struct amd_iommu *iommu, + struct iommu_dev_data *dev_data, + struct dev_table_entry *new); =20 #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index fad74d2bc1b1..3f2c61509b60 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -132,8 +132,9 @@ static void write_dte_lower128(struct dev_table_entry *= ptr, struct dev_table_ent * This function is used only by code, which updates DMA translation part = of the DTE. * So, only consider control bits related to DMA when updating the entry. */ -static void update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *= dev_data, - struct dev_table_entry *new) +void amd_iommu_update_dte256(struct amd_iommu *iommu, + struct iommu_dev_data *dev_data, + struct dev_table_entry *new) { unsigned long flags; struct dev_table_entry *dev_table =3D get_dev_table(iommu); @@ -413,7 +414,7 @@ static int clone_alias(struct pci_dev *pdev, u16 alias,= void *data) ret =3D -EINVAL; goto out; } - update_dte256(iommu, alias_data, &new); + amd_iommu_update_dte256(iommu, alias_data, &new); =20 amd_iommu_set_rlookup_table(iommu, alias); out: @@ -2109,7 +2110,7 @@ static void set_dte_entry(struct amd_iommu *iommu, =20 set_dte_gcr3_table(iommu, dev_data, &new); =20 - update_dte256(iommu, dev_data, &new); + amd_iommu_update_dte256(iommu, dev_data, &new); =20 /* * A kdump kernel might be replacing a domain ID that was copied from @@ -2130,7 +2131,7 @@ static void clear_dte_entry(struct amd_iommu *iommu, = struct iommu_dev_data *dev_ struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; =20 make_clear_dte(dev_data, dte, &new); - update_dte256(iommu, dev_data, &new); + amd_iommu_update_dte256(iommu, dev_data, &new); } =20 /* Update and flush DTE for the given device */ --=20 2.34.1 From nobody Wed Oct 1 21:23:23 2025 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012010.outbound.protection.outlook.com [52.101.43.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77A9026D4CA for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:47.9323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b8a04b7-8fa9-45bc-cbdd-08de00b143cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5656 Content-Type: text/plain; charset="utf-8" To allow reuse in other files in subsequent patches. Also, remove unused function parameter ptr. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 7 +++++++ drivers/iommu/amd/iommu.c | 13 ++----------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index eb46e8914eaf..c7cb4a80d44a 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -193,5 +193,12 @@ int amd_iommu_device_flush_dte(struct iommu_dev_data *= dev_data); void amd_iommu_update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, struct dev_table_entry *new); +static inline void +amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table= _entry *new) +{ + /* All existing DTE must have V bit set */ + new->data128[0] =3D DTE_FLAG_V; + new->data128[1] =3D 0; +} =20 #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 3f2c61509b60..386ac96b2c02 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2008,14 +2008,6 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_= data, ioasid_t pasid) return ret; } =20 -static void make_clear_dte(struct iommu_dev_data *dev_data, struct dev_tab= le_entry *ptr, - struct dev_table_entry *new) -{ - /* All existing DTE must have V bit set */ - new->data128[0] =3D DTE_FLAG_V; - new->data128[1] =3D 0; -} - /* * Note: * The old value for GCR3 table and GPT have been cleared from caller. @@ -2068,7 +2060,7 @@ static void set_dte_entry(struct amd_iommu *iommu, else domid =3D domain->id; =20 - make_clear_dte(dev_data, dte, &new); + amd_iommu_make_clear_dte(dev_data, &new); =20 if (domain->iop.mode !=3D PAGE_MODE_NONE) new.data[0] |=3D iommu_virt_to_phys(domain->iop.root); @@ -2128,9 +2120,8 @@ static void set_dte_entry(struct amd_iommu *iommu, static void clear_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data= *dev_data) { struct dev_table_entry new =3D {}; - struct dev_table_entry *dte =3D &get_dev_table(iommu)[dev_data->devid]; =20 - make_clear_dte(dev_data, dte, &new); + amd_iommu_make_clear_dte(dev_data, &new); amd_iommu_update_dte256(iommu, dev_data, &new); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:53.8576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d9f4cd6-ff57-41c3-e4f9-08de00b14756 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4043 Content-Type: text/plain; charset="utf-8" To allow reuse in other files in subsequent patches Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c7cb4a80d44a..d533bb8851ea 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -187,6 +187,7 @@ void amd_iommu_domain_set_pgtable(struct protection_dom= ain *domain, u64 *root, int mode); struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); +int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 /* DTE */ int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 386ac96b2c02..e0bfcda678a8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1392,7 +1392,7 @@ static int iommu_queue_command(struct amd_iommu *iomm= u, struct iommu_cmd *cmd) * This function queues a completion wait command into the command * buffer of an IOMMU */ -static int iommu_completion_wait(struct amd_iommu *iommu) +int amd_iommu_completion_wait(struct amd_iommu *iommu) { struct iommu_cmd cmd; unsigned long flags; @@ -1431,7 +1431,7 @@ static void domain_flush_complete(struct protection_d= omain *domain) * We need to wait for completion of all commands. */ xa_for_each(&domain->iommu_array, i, pdom_iommu_info) - iommu_completion_wait(pdom_iommu_info->iommu); + amd_iommu_completion_wait(pdom_iommu_info->iommu); } =20 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) @@ -1449,7 +1449,7 @@ static void iommu_flush_dte_sync(struct amd_iommu *io= mmu, u16 devid) =20 ret =3D iommu_flush_dte(iommu, devid); if (!ret) - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) @@ -1460,7 +1460,7 @@ static void amd_iommu_flush_dte_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; ++devid) iommu_flush_dte(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 /* @@ -1479,7 +1479,7 @@ static void amd_iommu_flush_tlb_all(struct amd_iommu = *iommu) iommu_queue_command(iommu, &cmd); } =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) @@ -1490,7 +1490,7 @@ static void amd_iommu_flush_tlb_domid(struct amd_iomm= u *iommu, u32 dom_id) dom_id, IOMMU_NO_PASID, false); iommu_queue_command(iommu, &cmd); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_all(struct amd_iommu *iommu) @@ -1500,7 +1500,7 @@ static void amd_iommu_flush_all(struct amd_iommu *iom= mu) build_inv_all(&cmd); =20 iommu_queue_command(iommu, &cmd); - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) @@ -1523,7 +1523,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; devid++) iommu_flush_irt(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 void amd_iommu_flush_all_caches(struct amd_iommu *iommu) @@ -1748,7 +1748,7 @@ void amd_iommu_dev_flush_pasid_pages(struct iommu_dev= _data *dev_data, if (dev_data->ats_enabled) device_flush_iotlb(dev_data, address, size, pasid, true); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void dev_flush_pasid_all(struct iommu_dev_data *dev_data, @@ -2137,7 +2137,7 @@ static void dev_update_dte(struct iommu_dev_data *dev= _data, bool set) =20 clone_aliases(iommu, dev_data->dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:10:59.6528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6c3ee97-530a-4586-296a-08de00b14acb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9232 Content-Type: text/plain; charset="utf-8" Introduce IOMMU_HWPT_DATA_AMD_GUEST data type for IOMMU guest page table, which is used for stage-1 in nested translation. The data structure contains information necessary for setting up the AMD HW-vIOMMU support. Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- include/uapi/linux/iommufd.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index efb52709c0a2..79d4ba43cd5f 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -455,16 +455,27 @@ struct iommu_hwpt_arm_smmuv3 { __aligned_le64 ste[2]; }; =20 +/** + * struct iommu_hwpt_amd_guest - AMD IOMMU specific user-managed + * guest I/O page table data + * @dte: Guest Device Table Entry (DTE) + */ +struct iommu_hwpt_amd_guest { + __aligned_u64 dte[4]; +}; + /** * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table + * @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE =3D 0, IOMMU_HWPT_DATA_VTD_S1 =3D 1, IOMMU_HWPT_DATA_ARM_SMMUV3 =3D 2, + IOMMU_HWPT_DATA_AMD_GUEST =3D 3, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:11:05.3165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24f20304-0829-44bf-35a1-08de00b14e2a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6878 Content-Type: text/plain; charset="utf-8" To support nested translation, the nest parent domain is allocated with IOMMU_HWPT_ALLOC_NEST_PARENT flag, and stores information of the v1 page table for stage 2 (i.e. GPA->SPA). Also, only support nest parent domain on AMD system, which can support the Guest CR3 Table (GCR3TRPMode) feature. This feature is required in order to program DTE[GCR3 Table Root Pointer] with the GPA. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 27 +++++++++++++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 556f1df32d53..d8c755b2045d 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -107,6 +107,7 @@ =20 =20 /* Extended Feature 2 Bits */ +#define FEATURE_GCR3TRPMODE BIT_ULL(3) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) =3D=3D 0x1) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index e0bfcda678a8..facee0f7a131 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2584,6 +2584,18 @@ do_iommu_domain_alloc(struct device *dev, u32 flags, return &domain->domain; } =20 +static inline bool is_nest_parent_supported(u32 flags) +{ + /* Only allow nest parent when these features are supported */ + if ((flags & IOMMU_HWPT_ALLOC_NEST_PARENT) && + (!check_feature(FEATURE_GT) || + !check_feature(FEATURE_GIOSUP) || + !check_feature2(FEATURE_GCR3TRPMODE))) + return false; + + return true; +} + static struct iommu_domain * amd_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags, const struct iommu_user_data *user_data) @@ -2591,15 +2603,22 @@ amd_iommu_domain_alloc_paging_flags(struct device *= dev, u32 flags, { struct amd_iommu *iommu =3D get_amd_iommu_from_dev(dev); const u32 supported_flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING | - IOMMU_HWPT_ALLOC_PASID; + IOMMU_HWPT_ALLOC_PASID | + IOMMU_HWPT_ALLOC_NEST_PARENT; =20 - if ((flags & ~supported_flags) || user_data) + if ((flags & ~supported_flags) || user_data || !is_nest_parent_supported(= flags)) return ERR_PTR(-EOPNOTSUPP); =20 switch (flags & supported_flags) { case IOMMU_HWPT_ALLOC_DIRTY_TRACKING: - /* Allocate domain with v1 page table for dirty tracking */ - if (!amd_iommu_hd_support(iommu)) + case IOMMU_HWPT_ALLOC_NEST_PARENT: + case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT: + /* + * Allocate domain with v1 page table for dirty tracking + * and/or Nest parent. + */ + if ((flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING) && + !amd_iommu_hd_support(iommu)) break; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:11:16.4807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2bb944a-bdd0-4292-cf99-08de00b154d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" The nested domain is allocated with IOMMU_DOMAIN_NESTED type to store stage-1 translation (i.e. GVA->GPA). This includes the GCR3 root pointer table along with guest page tables. The struct iommu_hwpt_amd_guest contains this information, and is passed from user-space as a parameter of the struct iommu_ops.domain_alloc_nested(). Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 5 +++ drivers/iommu/amd/amd_iommu_types.h | 33 +++++++++----- drivers/iommu/amd/iommu.c | 14 +++++- drivers/iommu/amd/nested.c | 67 +++++++++++++++++++++++++++++ 5 files changed, 109 insertions(+), 12 deletions(-) create mode 100644 drivers/iommu/amd/nested.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index 5ae46d99a45b..afa12ca2110e 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D iommu.o init.o quirks.o io_pgtable.o io_pgtable_v2.o ppr.o pasi= d.o -obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o +obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o nested.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) +=3D debugfs.o diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index d533bb8851ea..cc1f14899dfe 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -8,6 +8,7 @@ #define AMD_IOMMU_H =20 #include +#include =20 #include "amd_iommu_types.h" =20 @@ -202,4 +203,8 @@ amd_iommu_make_clear_dte(struct iommu_dev_data *dev_dat= a, struct dev_table_entry new->data128[1] =3D 0; } =20 +/* NESTED */ +struct iommu_domain * +amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags, + const struct iommu_user_data *user_data); #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index d8c755b2045d..ba27fad77b57 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -20,6 +20,8 @@ #include #include =20 +#include + /* * Maximum number of IOMMUs supported */ @@ -604,6 +606,25 @@ struct protection_domain { struct list_head dev_data_list; /* List of pdom_dev_data */ }; =20 +/* + * Structure defining one entry in the device table + */ +struct dev_table_entry { + union { + u64 data[4]; + u128 data128[2]; + }; +}; + +/* + * Nested domain is specifically used for nested translation + */ +struct nested_domain { + struct iommu_domain domain; /* generic domain handle used by iommu core c= ode */ + u16 id; /* the domain id written to the device table = */ + struct dev_table_entry guest_dte; /* Guest vIOMMU DTE */ +}; + /* * This structure contains information about one PCI segment in the system. */ @@ -857,6 +878,8 @@ struct iommu_dev_data { struct list_head list; /* For domain->dev_list */ struct llist_node dev_data_list; /* For global dev_data_list */ struct protection_domain *domain; /* Domain the device is bound to */ + struct protection_domain *parent; /* Parent Domain the device is bound to= */ + struct nested_domain *ndom; /* Nested Domain the device is bound to= */ struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */ struct device *dev; u16 devid; /* PCI Device ID */ @@ -894,16 +917,6 @@ extern struct list_head amd_iommu_pci_seg_list; */ extern struct list_head amd_iommu_list; =20 -/* - * Structure defining one entry in the device table - */ -struct dev_table_entry { - union { - u64 data[4]; - u128 data128[2]; - }; -}; - /* * Structure defining one entry in the command buffer */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index facee0f7a131..c1abb06126c1 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2613,6 +2613,9 @@ amd_iommu_domain_alloc_paging_flags(struct device *de= v, u32 flags, case IOMMU_HWPT_ALLOC_DIRTY_TRACKING: case IOMMU_HWPT_ALLOC_NEST_PARENT: case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT: + { + struct iommu_domain *dom; + /* * Allocate domain with v1 page table for dirty tracking * and/or Nest parent. @@ -2620,7 +2623,16 @@ amd_iommu_domain_alloc_paging_flags(struct device *d= ev, u32 flags, if ((flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING) && !amd_iommu_hd_support(iommu)) break; - return do_iommu_domain_alloc(dev, flags, PD_MODE_V1); + + dom =3D do_iommu_domain_alloc(dev, flags, PD_MODE_V1); + if (!IS_ERR_VALUE(dom) && + (flags & IOMMU_HWPT_ALLOC_NEST_PARENT)) { + struct iommu_dev_data *dev_data =3D dev_iommu_priv_get(dev); + + dev_data->parent =3D to_pdomain(dom); + } + return dom; + } case IOMMU_HWPT_ALLOC_PASID: /* Allocate domain with v2 page table if IOMMU supports PASID. */ if (!amd_iommu_pasid_supported()) diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c new file mode 100644 index 000000000000..11a0237174bb --- /dev/null +++ b/drivers/iommu/amd/nested.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#define pr_fmt(fmt) "AMD-Vi: " fmt +#define dev_fmt(fmt) pr_fmt(fmt) + +#include + +#include "amd_iommu.h" +#include "amd_iommu_types.h" + +static const struct iommu_domain_ops nested_domain_ops =3D { + .free =3D amd_iommu_domain_free, +}; + +static inline struct nested_domain *to_ndomain(struct iommu_domain *dom) +{ + return container_of(dom, struct nested_domain, domain); +} + +struct iommu_domain * +amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags, + const struct iommu_user_data *user_data) +{ + int ret; + struct iommu_hwpt_amd_guest gdte; + struct nested_domain *ndom; + + if (user_data->type !=3D IOMMU_HWPT_DATA_AMD_GUEST) + return ERR_PTR(-EOPNOTSUPP); + + /* + * Need to make sure size of struct iommu_hwpt_amd_guest and + * struct dev_table_entry are the same since it will be copied + * from one to the other later on. + */ + if (WARN_ON(sizeof(struct dev_table_entry) !=3D sizeof(gdte))) + return ERR_PTR(-EINVAL); + + ret =3D iommu_copy_struct_from_user(&gdte, user_data, + IOMMU_HWPT_DATA_AMD_GUEST, + dte); + if (ret) + return ERR_PTR(ret); + + ndom =3D kzalloc(sizeof(*ndom), GFP_KERNEL); + if (IS_ERR(ndom)) + return ERR_PTR(-ENOMEM); + + ndom->domain.ops =3D &nested_domain_ops; + ndom->domain.type =3D IOMMU_DOMAIN_NESTED; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:11:17.1936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3ffb062-3e2c-4190-941c-08de00b1553e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8906 Content-Type: text/plain; charset="utf-8" Introduce set_dte_nested() to program guest translation settings in the host DTE when attaches the nested domain to a device. Also, enable the GCR3TRPMode feature when supported. Note that nested translation is only supported with the GCR3TRP mode. When it is enabled, the AMD IOMMU driver programs the GCR3 Table Root Pointer field of the device table entry with the GPA provided by the guest. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 + drivers/iommu/amd/amd_iommu_types.h | 3 + drivers/iommu/amd/init.c | 3 + drivers/iommu/amd/nested.c | 111 +++++++++++++++++++++++++++- 4 files changed, 116 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index cc1f14899dfe..924152973d11 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -190,6 +190,8 @@ struct dev_table_entry *get_dev_table(struct amd_iommu = *iommu); struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid); int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 +extern bool amd_iommu_snp_en; + /* DTE */ int amd_iommu_device_flush_dte(struct iommu_dev_data *dev_data); void amd_iommu_update_dte256(struct amd_iommu *iommu, diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index ba27fad77b57..9bc2e0e18978 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -188,6 +188,7 @@ #define CONTROL_EPH_EN 45 #define CONTROL_XT_EN 50 #define CONTROL_INTCAPXT_EN 51 +#define CONTROL_GCR3TRPMODE 58 #define CONTROL_IRTCACHEDIS 59 #define CONTROL_SNPAVIC_EN 61 =20 @@ -417,6 +418,8 @@ #define DTE_FLAG_V BIT_ULL(0) #define DTE_FLAG_TV BIT_ULL(1) #define DTE_FLAG_HAD (3ULL << 7) +#define DTE_MODE_MASK GENMASK_ULL(11, 9) +#define DTE_FLAG_PPR BIT_ULL(52) #define DTE_FLAG_GIOV BIT_ULL(54) #define DTE_FLAG_GV BIT_ULL(55) #define DTE_GLX GENMASK_ULL(57, 56) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f2991c11867c..c45a4bd89569 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1122,6 +1122,9 @@ static void iommu_enable_gt(struct amd_iommu *iommu) return; =20 iommu_feature_enable(iommu, CONTROL_GT_EN); + + if (check_feature2(FEATURE_GCR3TRPMODE)) + iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE); } =20 /* sets a specific bit in the device table entry. */ diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c index 11a0237174bb..5a0c369ba283 100644 --- a/drivers/iommu/amd/nested.c +++ b/drivers/iommu/amd/nested.c @@ -11,9 +11,7 @@ #include "amd_iommu.h" #include "amd_iommu_types.h" =20 -static const struct iommu_domain_ops nested_domain_ops =3D { - .free =3D amd_iommu_domain_free, -}; +static const struct iommu_domain_ops nested_domain_ops; =20 static inline struct nested_domain *to_ndomain(struct iommu_domain *dom) { @@ -65,3 +63,110 @@ amd_iommu_alloc_domain_nested(struct iommufd_viommu *vi= ommu, u32 flags, kfree(ndom); return ERR_PTR(ret); } + +static void set_dte_nested(struct amd_iommu *iommu, + struct dev_table_entry *gdte, + struct nested_domain *ndom, + struct iommu_dev_data *dev_data) +{ + struct dev_table_entry *initial_dte; + struct dev_table_entry new =3D {0}; + struct protection_domain *pdom =3D dev_data->parent; + + if (WARN_ON(!ndom || !pdom || (pdom->iop.mode =3D=3D PAGE_MODE_NONE))) + return; + + amd_iommu_make_clear_dte(dev_data, &new); + + new.data[0] |=3D iommu_virt_to_phys(pdom->iop.root); + new.data[0] |=3D FIELD_PREP(DTE_MODE_MASK, pdom->iop.mode); + new.data[0] |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV; + new.data[0] |=3D (DTE_FLAG_PPR & gdte->data[0]); + + if (pdom->dirty_tracking) + new.data[0] |=3D DTE_FLAG_HAD; + + if (dev_data->ats_enabled) + new.data[1] |=3D DTE_FLAG_IOTLB; + + /* + * Use nested domain ID to program DTE. + * See amd_iommu_alloc_domain_nested(). + */ + new.data[1] |=3D ndom->id; + + /* + * Restore cached persistent DTE bits, which can be set by information + * in IVRS table. See set_dev_entry_from_acpi(). + */ + initial_dte =3D amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data= ->devid); + if (initial_dte) { + new.data128[0] |=3D initial_dte->data128[0]; + new.data128[1] |=3D initial_dte->data128[1]; + } + + /* Guest translation stuff */ + new.data[0] |=3D (gdte->data[0] & + (DTE_GLX | DTE_FLAG_GV | DTE_FLAG_GIOV)); + + /* GCR3 table */ + new.data[0] |=3D (gdte->data[0] & DTE_GCR3_14_12); + new.data[1] |=3D (gdte->data[1] & (DTE_GCR3_30_15 | DTE_GCR3_51_31)); + + /* Guest paging mode */ + new.data[2] |=3D (gdte->data[2] & DTE_GPT_LEVEL_MASK); + + amd_iommu_update_dte256(iommu, dev_data, &new); +} + +static int nested_attach_device(struct iommu_domain *dom, struct device *d= ev) +{ + struct iommu_dev_data *dev_data =3D dev_iommu_priv_get(dev); + struct amd_iommu *iommu =3D get_amd_iommu_from_dev_data(dev_data); + struct nested_domain *ndom =3D to_ndomain(dom); + struct dev_table_entry *gdte =3D &ndom->guest_dte; + int ret =3D 0; + + if (dev_data->ndom =3D=3D ndom) + return ret; + + if (!dev_is_pci(dev)) + return -EINVAL; + + /* Currently only support GCR3TRPMode with nested translation */ + if (!check_feature2(FEATURE_GCR3TRPMODE)) + return -EOPNOTSUPP; + + /* We need to check host capability before setting the mode */ + if ((FIELD_GET(DTE_GPT_LEVEL_MASK, gdte->data[2]) =3D=3D GUEST_PGTABLE_5_= LEVEL) && + (amd_iommu_gpt_level < PAGE_MODE_5_LEVEL)) + return -EOPNOTSUPP; + + WARN_ON(dev_data->ndom); + + dev_data->ndom =3D ndom; + + mutex_lock(&dev_data->mutex); + + /* Update device table entry */ + set_dte_nested(iommu, gdte, ndom, dev_data); + amd_iommu_device_flush_dte(dev_data); + amd_iommu_completion_wait(iommu); + + mutex_unlock(&dev_data->mutex); + + return ret; +} + +static void nested_domain_free(struct iommu_domain *dom) +{ + struct nested_domain *ndom =3D to_ndomain(dom); + + amd_iommu_pdom_id_free(ndom->id); + kfree(ndom); +} + +static const struct iommu_domain_ops nested_domain_ops =3D { + .attach_dev =3D nested_attach_device, + .free =3D nested_domain_free, +}; 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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SA2PEPF00003AE7.mail.protection.outlook.com (10.167.248.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9182.15 via Frontend Transport; Wed, 1 Oct 2025 06:11:22 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 30 Sep 2025 23:11:16 -0700 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 12/12] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Date: Wed, 1 Oct 2025 06:09:54 +0000 Message-ID: <20251001060954.5030-13-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251001060954.5030-1-suravee.suthikulpanit@amd.com> References: <20251001060954.5030-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|PH8PR12MB6892:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bbfc1ea-afdc-4f03-d0f7-08de00b15857 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2025 06:11:22.3811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bbfc1ea-afdc-4f03-d0f7-08de00b15857 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6892 Content-Type: text/plain; charset="utf-8" Introduce struct amd_iommu_vminfo to store AMD HW-vIOMMU per-IOMMU data, which is initialized when calling struct iommu_ops.viommu_init(). Currently, the struct amd_iommu_vminfo and amd_iommu_viommu_init() contain base code to support nested domain allocation for vIOMMU using the struct iommufd_viommu_ops.alloc_domain_nested. Additional initialization will be added in subsequent patches. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 10 +++++ drivers/iommu/amd/amd_iommu_types.h | 6 +++ drivers/iommu/amd/iommu.c | 61 ++++++++++++++++++++++++++++- drivers/iommu/amd/iommufd.c | 8 ++++ drivers/iommu/amd/iommufd.h | 2 + include/uapi/linux/iommufd.h | 19 +++++++++ 6 files changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 924152973d11..6cb929b657e4 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -169,6 +169,16 @@ static inline struct amd_iommu *get_amd_iommu_from_dev= _data(struct iommu_dev_dat return iommu_get_iommu_dev(dev_data->dev, struct amd_iommu, iommu); } =20 +static inline struct amd_iommu *get_amd_iommu_from_devid(u16 devid) +{ + struct amd_iommu *iommu; + + for_each_iommu(iommu) + if (iommu->devid =3D=3D devid) + return iommu; + return NULL; +} + static inline struct protection_domain *to_pdomain(struct iommu_domain *do= m) { return container_of(dom, struct protection_domain, domain); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 9bc2e0e18978..dcecb5df2f72 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -1117,6 +1118,11 @@ struct amd_irte_ops { void (*clear_allocated)(struct irq_remap_table *, int); }; =20 +struct amd_iommu_vminfo { + struct iommufd_viommu core; + u32 iommu_devid; +}; + #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index c1abb06126c1..e3503091cd65 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3063,6 +3063,61 @@ static const struct iommu_dirty_ops amd_dirty_ops = =3D { .read_and_clear_dirty =3D amd_iommu_read_and_clear_dirty, }; =20 +static size_t amd_iommu_get_viommu_size(struct device *dev, enum iommu_vio= mmu_type viommu_type) +{ + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_AMD) + return 0; + + return VIOMMU_STRUCT_SIZE(struct amd_iommu_vminfo, core); +} + +/* + * This is called from the drivers/iommu/iommufd/viommu.c: iommufd_viommu_= alloc_ioctl + */ +static int amd_iommu_viommu_init(struct iommufd_viommu *viommu, + struct iommu_domain *parent, + const struct iommu_user_data *user_data) +{ +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + int ret; + struct amd_iommu *iommu; + struct iommu_viommu_amd data; + struct amd_iommu_vminfo *vminfo =3D container_of(viommu, struct amd_iommu= _vminfo, core); + + if (!user_data) + return -EINVAL; + + ret =3D iommu_copy_struct_from_user(&data, user_data, + IOMMU_VIOMMU_TYPE_AMD, + reserved); + if (ret) + return ret; + + iommu =3D get_amd_iommu_from_devid(data.iommu_devid); + if (!iommu) + return -ENODEV; + + vminfo->iommu_devid =3D data.iommu_devid; + + /* TODO: Add AMD HW-vIOMMU initialization code */ + + ret =3D iommu_copy_struct_to_user(user_data, &data, + IOMMU_VIOMMU_TYPE_AMD, + reserved); + if (ret) + goto err_out; + + viommu->ops =3D &amd_viommu_ops; + + return 0; + +err_out: + return ret; +#else + return -EOPNOTSUPP; +#endif /* CONFIG_AMD_IOMMU_IOMMUFD */ +} + const struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, .hw_info =3D amd_iommufd_hw_info, @@ -3088,7 +3143,11 @@ const struct iommu_ops amd_iommu_ops =3D { .iotlb_sync =3D amd_iommu_iotlb_sync, .free =3D amd_iommu_domain_free, .enforce_cache_coherency =3D amd_iommu_enforce_cache_coherency, - } + }, + + /* For VIOMMU */ + .get_viommu_size =3D amd_iommu_get_viommu_size, + .viommu_init =3D amd_iommu_viommu_init, }; =20 #ifdef CONFIG_IRQ_REMAP diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 72eaaa923d04..d81e4ad17d9d 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -29,3 +29,11 @@ void *amd_iommufd_hw_info(struct device *dev, u32 *lengt= h, u32 *type) =20 return hwinfo; } + +/* + * See include/linux/iommufd.h + * struct iommufd_viommu_ops - vIOMMU specific operations + */ +const struct iommufd_viommu_ops amd_viommu_ops =3D { + .alloc_domain_nested =3D amd_iommu_alloc_domain_nested, +}; diff --git a/drivers/iommu/amd/iommufd.h b/drivers/iommu/amd/iommufd.h index f880be80a30d..0d59ef160780 100644 --- a/drivers/iommu/amd/iommufd.h +++ b/drivers/iommu/amd/iommufd.h @@ -7,6 +7,8 @@ #define AMD_IOMMUFD_H =20 #if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) +extern const struct iommufd_viommu_ops amd_viommu_ops; + void *amd_iommufd_hw_info(struct device *dev, u32 *length, u32 *type); #else #define amd_iommufd_hw_info NULL diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 79d4ba43cd5f..e7084dbc5c95 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1038,11 +1038,13 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for= ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_AMD: AMD HW-vIOMMU type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT =3D 0, IOMMU_VIOMMU_TYPE_ARM_SMMUV3 =3D 1, IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV =3D 2, + IOMMU_VIOMMU_TYPE_AMD =3D 3, }; =20 /** @@ -1061,6 +1063,23 @@ struct iommu_viommu_tegra241_cmdqv { __aligned_u64 out_vintf_mmap_length; }; =20 +/** + * struct iommu_viommu_amd - AMD vIOMMU Interface (IOMMU_VIOMMU_TYPE_AMD) + * @iommu_devid: Host IOMMU PCI device ID + * @viommu_devid: Guest vIOMMU PCI device ID + * @trans_devid: GPA->GVA translation device ID (host) + * @out_gid: (out) Guest ID + * @out_vfmmio_mmap_offset: (out) mmap offset for vIOMMU VF-MMIO + */ +struct iommu_viommu_amd { + __u32 iommu_devid; + __u32 viommu_devid; + __u32 trans_devid; + __u32 out_gid; + __aligned_u64 out_vfmmio_mmap_offset; + __u32 reserved; /* must be last */ +}; + /** * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC) * @size: sizeof(struct iommu_viommu_alloc) --=20 2.34.1