From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 278771547F2; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=tvcxql/3LXuxo2gnPTsoVIze0WmNGnqHNuvfA7IE0p061ey02Ut87oXLENUv6wG09sCYv3PS+CIQ+4jdYaiGLQyFtQAkj2H2MmwMXCHuPD+/gZ6wdHxM3SvJhJIouSuSi/M5Tm9MFR75pAK3/Wx7W0vfiUjS++BVX4CFUDkPh/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=DcwuyX8vW2kqJZ7nlBXFHvGPhvHT+XYW91wlJclysz4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NlfV2qJyNB60E5Ha3ZL4yfcaMLyGf91KkDMrAsVzSP9DvJCgfmw5WquGfSs5zdzcbZS47eIZ03D0Fw/kE67tMUzLgukiBn53kjgfbXuAms48WrLMzhfNy93q2orCu7zwFcOUDU6HFHufWBySir1tPPMSGxizg30unwfs1xTkXM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dw+WDp7t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dw+WDp7t" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0663BC4CEF9; Wed, 1 Oct 2025 14:04:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=DcwuyX8vW2kqJZ7nlBXFHvGPhvHT+XYW91wlJclysz4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dw+WDp7tfCs/HdgNqdsMHlB2nMh3x8+mTmXTaPGGQR52J7hnBEZujO3BlSWmebkQu cXwawYWSr2HuNu2zLs79BUGij2t4JBAE9j/ABBH3jzr3RpTJ6GQXr9d5CgH5q7yqfb Mme06hyKYJ5YP5iX0EyEAdkER96vSobhNJNWhF88yzqOkC5ZfBKxJ5J65UKjzszOGb BtEHQz1ZwQ4GcJj2s8Idf4y14vS+DXxnzG4GIT1dCS+bji2cmRTuKYZhjz1W2pDCgJ LaHaCcyZEJzt66B70BmJL1SH6HqgxGvuwwpqjx4uxqJb6OnVYJjnbkkK9BPL574A4u TKhUaFE4QHi2g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E347CCAC5BB; Wed, 1 Oct 2025 14:04:22 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:17 +0400 Subject: [PATCH v16 1/9] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-1-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Devi Priya , Krzysztof Kozlowski , Baruch Siach , Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1766; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=TIgQXfGvQp7H4uzUZyQsZZpdMSae9nM97ANzvYRj3gc=; b=XaG2XNit7oo8lR7gdorPFnH0Ww9dnr+Pi96LwXAiOjPFL+WQwpLo9hCKoijz1+QuFaEfWh1v/ 8VBy6ez2YO3BWj/OXxkNspVoUeztQJR518JzrPZNHdy3aVTs+hFNY+m X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 44 ++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1172f0b53fadc140482f9384a36= 020260df372b7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + compatible: + const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + }; --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ABF12EAB8E; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=ZZuwBHpyM7VsdnMhR28ntczU3DqVWQwa/OPm8t8MpIQLaD69bzOXc5SLdLDG8FkOepza0Fq8BGQ/lA1adEdnQouM3iKx5ahZ6ydcrVfsEYg8PpeH5wKoOvjvI8qmyXzHFGcGCQ1g0in6djxa3OnXn4r3QKVRnkirw9lkCrviF8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=VG28xTxL7HN7Fm1A0GthPKfLu9yBtVAI+DO+fHgRXBY=; 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Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:18 +0400 Subject: [PATCH v16 2/9] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-2-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Devi Priya , Baruch Siach , George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=10027; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Hdqt8/DUmRi2xcLVyT6bRUJrJ2PqVNC6Tf6KU6AbUHA=; b=qvosQ0jpd2phRs5d0nczBBIebso39yQZW/ImtIE10gRWcCgeyhSRTYxRzGnJ3gQmgijf1LMu1 bqa41UvibRsBLeYkAy+wRSa7lSOmktCcVToqJflubWCQAvmelvPw8rE X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- v16: Simplified code to calculate divs and duty cycle as per Uwe's comments Removed unused pwm_chip struct from ipq_pwm_chip struct Removed unnecessary cast as per Uwe's comment Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled Replaced pwmchip_add by devm_pwmchip_add and removed .remove function Removed .owner from driver struct v15: No change v14: Picked up the R-b tag v13: Updated the file name to match the compatible Sorted the properties and updated the order in the required field Dropped the syscon node from examples v12: Picked up the R-b tag v11: No change v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-K=C3=B6nig) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 214 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 227 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c2fd3f4b62d9ea422a51a73fa87dc7a73703ebaf..33ac49251b3cc957bc356aa3919= 9b748577d295f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -337,6 +337,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index dfa8b4966ee19af18ea47080db4adf96c326f3d7..74e07f654d43dfee83e7bb3a49e= 41acf8ae011fc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 0000000000000000000000000000000000000000..f1b195de3a6ddb0501256581c28= 213ab33da6716 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to clock rate */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field + */ +#define IPQ_PWM_MAX_DIV 0xFFFF + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to reflect the changed divider and high duration + * values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + struct clk *clk; + void __iomem *mem; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_d= iv, + unsigned int pwm_div, unsigned long rate, u64 duty_ns, + bool enable) +{ + unsigned long hi_dur; + unsigned long val =3D 0; + + /* + * high duration =3D pwm duty * (pwm div + 1) + * pwm duty =3D duty_ns / period_ns + */ + hi_dur =3D div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (enable) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) + return -ERANGE; + + if ((unsigned long long)rate > 16ULL * GIGA) + return -EINVAL; + + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + /* Restrict pwm_div to 0xfffe for fine-grained duty cycle */ + pwm_div =3D IPQ_PWM_MAX_DIV - 1; + /* Compute pre_div with rounding up to ensure accurate period */ + pre_div =3D DIV64_U64_ROUND_UP(period_ns * rate, (u64)NSEC_PER_SEC * (pwm= _div + 1)); + + if (pre_div > IPQ_PWM_MAX_DIV) + return -ERANGE; + + /* Configure divider and duty cycle */ + config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + + state->polarity =3D PWM_POLARITY_NORMAL; + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + /* No overflow here, both pre_div and pwm_div <=3D 0xffff */ + effective_div =3D (pre_div + 1) * (pwm_div + 1); + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "regs map failed"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "failed to get clock"); + + chip->ops =3D &ipq_pwm_ops; + chip->npwm =3D 4; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add pwm chip\n"); + + return ret; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BAA130215F; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-3-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1027; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=A2Jt3NeWTdpQUpS3pQ9NsEueZ+KtHb8levqoaMhjNmE=; b=3L68oXSys8aKJlQ15Z266p5eTIw9pGZs79GlDUpJDiS2JOTpA+W/RtFIoTT6gxDo3nZJM/sxv FcgFBymqjy8CNJBuIQ2eKZOAHHYxf2jYWMN7ADL48OCGP/2YE8xTXWx X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ5018 and use IPQ6018 as the fallback. Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index 1172f0b53fadc140482f9384a36020260df372b7..acbdd952fcca53368e3b594544d= f8d3dae8a06b3 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -11,7 +11,12 @@ maintainers: =20 properties: compatible: - const: qcom,ipq6018-pwm + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm =20 reg: maxItems: 1 --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DD603019C5; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=IWfLBq5zJSTYI8Iv9TJeEPOZnJ3UI91NjCVVvTcTVA2H0J52SnWZvdJF0mxmG9gVYWVauNc41+9jQTvlfexC8NUvqBFIv0ZU7HsgZRXUzEb6I9XATptXf3/K5IMnXZzEFhsWJE6Yf6//CWdngc+0Y7rlQ4xgMRlIK7vxdDwYzZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=uxRiHy8P3s8sW7vDoa08TCwgTgT1biPZKyz5CO7SMNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l4A3plsbkOVj0mCyNESuoCSWlG1LrvTWXKq2dpf8wuCzUbfClVX8RaKvo0YT7wMDt3s8lAItcLA2t0rsuUJosixn+UI8YDrymTAqZ+SihCQvVRPROY0Z7s/+6BAvsgHo3KGadwaOsead2JrU5kFdVfLH9JyJWcl2QXogv+FFSgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lKc/wIOu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lKc/wIOu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 315E8C4CEFB; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=uxRiHy8P3s8sW7vDoa08TCwgTgT1biPZKyz5CO7SMNE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lKc/wIOuTPr1TiEx6kJ57y3NgDdyN08flnrB33vok1ggmg1s+U3wdEfrVBKP1K1cE rQrTrqJGw2Ldwv7XYiNl+c0MrlWdryRD9Rb9EtT2t60t7gCVOaytWEGoX3e6b0puJr UAlsTM0MkyMTCK8dnh8B/e1FMWAs+Sfa+gBcQlPdaGDnZyi320Srp94MyOED7OXPmv ytDwxaqrdkXwr3npO45yKvAntk6kUDIGZuzM/P5hVO2okxztM4C0v1eIKEXHf9Sw3f 46vGgf8lib43pObBp0UGgH1dioHwr0XTgLvkYUCYRPFhBNgUmpPX+JdNTGeBVN7a4a FqLBPvy2w8Hpg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21E07CCD180; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:20 +0400 Subject: [PATCH v16 4/9] dt-bindings: pwm: qcom,ipq6018-pwm: Add compatible for ipq5332 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-4-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=935; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y8giwJKpFzWeiaRvUor0Eljp/p0jcgEG1QTHLcQUb/c=; b=cbOuQtetQFcdRwCz4KSHRK5SusXPEgOjS3eOsqWGIPHrIZhGq3M+OYdYqr+WgdT6Bipe37jmd OZ/TQIRAkdaBT0x38hr3KQK1P01kvvaWsVvuGEs3AGM4Z7O64QMTsjn X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5332 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ5332 and use IPQ6018 as the fallback. Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index acbdd952fcca53368e3b594544df8d3dae8a06b3..e00b9e01f4f89dd0d08610772c9= 84a0e2725d154 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,ipq5018-pwm + - qcom,ipq5332-pwm - const: qcom,ipq6018-pwm - const: qcom,ipq6018-pwm =20 --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A78C0302175; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=VX27Uvgrt7W7OuZpjQvrt+IgeuBq1Toavl2GTKymh3zPGRrmj6cnab2Uo7l+xRG0ReqcodKIDMVQhtycRPemb3YHegQJGFP6Eo+DinwziokL7EhSiTI9Ga681ajAjfOBNll4gLQWRB200HRuMr9ytyFTtT/WjRQzmodQnjd6ORE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=WYgoggOlSv1+Tj61N1rXTFai3T7w6ajbAxxFTUFbrE8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lIFqNmh5a6YV43+pCfRoVP8Tdt1iFHqgA9NaeeF4niFqK3fYrM+Cpflsz+g+J9ilU8k5gNkml9luacMCELd152SFctPvJFwC0Yju5rjJYsomfGRKDSz4AuYfcfFv1prrJWMIrUGoZa0NO2kk4RrDRIs3dzDQvT3eabiH6ovszoI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rMuusYAH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rMuusYAH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3EAB0C4AF12; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=WYgoggOlSv1+Tj61N1rXTFai3T7w6ajbAxxFTUFbrE8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rMuusYAH5Wkw8RJMA7+367vFKAr6mm5yYacp3Gjekn4l7bP0/EQvraZZ+4vVaRpPu +5xfPb8ohVh3Avpbbocm+D8miOUyzYUzmDVeq9rUVuQbQEJE8cjacK0RV/3VN0zlfP P/0wYOo19bn98+6SzH7qIsUBlFRxIUuCq1ic1gHQO7nACcOMHAPDoL4cwsQPIZ4LF2 L0v9QgnAVlPHTwlCvfQmgt9uTxREgtvgEy+a4hgyL/yPmVPRq4hGyqjwNQyMGSEw85 bD6g3S9N9ze1xHSObO/KQGg0yZ0ZWm+qEe79U39QIzXBQry6B4h2FZUH3IOS2rqxBe LDMXgzkg2Up0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 304D4CCA472; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:21 +0400 Subject: [PATCH v16 5/9] dt-bindings: pwm: qcom,ipq6018-pwm: Add compatible for ipq9574 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-5-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=953; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=3YfcxJTNETA/GabL2m0Fbhu/ciUPosZ3L8BYDjaDExc=; b=yRSyQmclC8ef01qnB1fsqiaASk9xknsxKLAvZvJFodLDJbw1+ywGxqe6NbRuxd1QGwLqeAaki Cru/GuNHjuXDdT64OFhKonSTVOgWc87NLsqVFBnrvey4ecdpu/DOCxH X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ9574 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ9574 and use IPQ6018 as the fallback. Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index e00b9e01f4f89dd0d08610772c984a0e2725d154..48dd7d1b8f511b0dd2cbebc07f3= 3cafc3655ce50 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,ipq5018-pwm - qcom,ipq5332-pwm + - qcom,ipq9574-pwm - const: qcom,ipq6018-pwm - const: qcom,ipq6018-pwm =20 --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A58EE30216C; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=d1lFE4TB7kMAl86YDUpKq9Nq4OoCdxaFqgw4Iu1uJ9nAD+GPbc3a3Py9xC0GDMd3S1JxG67LuvBu5K19Fq1iSt7raR7Myhmlb6/WMNse1wbkhPxzmDnPNx2Jkf2gnW5oLIUoiABR+ZQpxyOoHu/BqJyw1wmgfpOcZZZVEq4sk4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=1jW/pw93M9ZTt2+XfXJpx1QIagE29diOB2yA8Z6Eh38=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QkClrZPnI4y2KpAPB+KB3SxswyqaWgRD3G4c9a6gIr7hhYBkM236d/Qelxfl5IDoyBt+b8GUUQGo0QDRK2mo5NxtN2Z+RR+MTIV0cO6Cw3lBmlISuCY4lz8GWuAkMUdQyWTKIU/LntGZwSjH+32dfzFc4QAFmebsytaFVz+shAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W1ENreQJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W1ENreQJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4BF4DC4CEFC; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=1jW/pw93M9ZTt2+XfXJpx1QIagE29diOB2yA8Z6Eh38=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=W1ENreQJE4iMsM0CPpOW4SnG4delAs6r9cuhlrUewNvglbGon8aHtQNcMTaW1eVUc s8/Soiupj2199EEOYXjowNvaDUCoBsJEA4+cjvNfmSIgLgUXPVOkjQ9uVSLjtkNlrO D987fCne/MpZmtlbUzcOtmQTGvBArb3bBjW5ax3AxtMx8wRuP9T4FBvAa7rqTdiie4 XdTx3N+K8HzLnAaTyAE6KWfjtigzk86ZU3H6GzABUo4ShttVjXwMxGh9lsmfbnOz2L CXTyrrrl7LQMY7PMbe3AzO0mxL67B5lwdPhANZHSP/u4tifYA2B/plrRMcg/tI1MpU jYBswvgaCi30A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F417CCA470; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:22 +0400 Subject: [PATCH v16 6/9] arm64: dts: qcom: ipq6018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-6-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Devi Priya , Krzysztof Kozlowski , Baruch Siach , George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1383; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=aXkvbG/7UnHwE6F120GhEEEi6SRmzhki3XGP6tCrgxM=; b=t8ayXSkiFsad3nxWe+r+nFkcDK7Nya2k4tZf9kbAnUAB7mNCwX2Io9rjCv9pDcvDb5ImcEatG pkxa5VPkC+WD0dlk/PHqpg9Jsp5vtaGrJw+0oY8TPEeSHoMvFW40vXv X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126eff3761430a47472b52d27f961040..84bc2dec2b22f9634d4ec926dae= ebb9b40cb112f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9205302176; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=US1qPVs1cZhvRarTLB50PVT3AknlyKsf5OorOvfqEyHNtijA9dqStkA5H2DTC48DdGQTOBOU0w1Wk0qIs+otEkiHfYi1/J+mgfgfrIm0t46R3FWxFW/adcy4MJyeZfGtAA4C/LRxQTAp582AUzXhsS2EfEGw5zdtG5Uk9s74m7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=Spr04DQ7XY9/ry1ZPrbDw96CNr3+u2z1MRgJct4ul8E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jTubPN3Rlhq0TmJXVHoxOrVQOObXm2qq474eIeN4FIErxWSJICb1ZyoEjZBsRGiogSytDSOItXWqLEpL5TCwk1dhuIjlFK5v64Kfioe0sM3oz/zx/4CFHBPX6LYiWiddFpCnn92srB9ZsGQTCGp/AymiBwefy5Kc0Y1TL5ubLVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hBbN2/eY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hBbN2/eY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5FDADC2BC86; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=Spr04DQ7XY9/ry1ZPrbDw96CNr3+u2z1MRgJct4ul8E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hBbN2/eYdbWYERly0xm93y5Z/TKc+HwqvnNH/JE+KFWQKDEqNYgpVnZmNc6TgSrgn sXFLDHJcJ+hwNF5GAHPYEILdP+BpEvF2bRVWQs1Wd+FI8CsvSHtLvxGiSj/KDKP4Z8 kUayAbGfUydkHcZUg6d5jGb63guCiz1h+B9DQeLR6sAEOuZojoPNh50rN+onsCM1Qq 5SoQhkJQS0QRDpT1jVt7nyUrgtiu9JkKLmPTFp0tkC0F/GIiT33GP4kkI+aR2engnc znleGYGfNA0EA/xRZ389Y9zZ/c2RDxdGroDOP0lgt0khcdD8gxKYkd8Xt3BMNSzVwA iTDS24GmTDuVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FCB5CCD180; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:23 +0400 Subject: [PATCH v16 7/9] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-7-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1166; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=ga1rBlYVYLnYBPfkk+/zhO3WBfe7APc074QH0n50Pa0=; b=arTo/hNHvUFsrep46RZGgDiY7pvvzaCrt7RPKJl3kmCSMSyMks2LdcYrAz0zWiECFbdcNmPhk 7ymOkWZqjLRBxrlGA8IX6ifSg8xwKt2LWBCDSOZab4ZeCRwAA2AiwrI X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index f024b3cba33f6100ac3f4d45598ff2356e026dcf..d4bdf2884aa7f73711cf8a37b7a= 4c4e7e54c503c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B49F630277F; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=iIO51GZ3Y9IcGB5DP0WJar7iSES7P6e37+k+lpy3AgJelpbK97INWnn7gKpoH7duj2Hjazx5truD3drwDxK80ztkwUZVwjxFCDTWNsFdPnOAbBtUPh6FLVn1JG46bPomw/oUtEY8c95RBYyQe1+Nl/na913wxX3Vy+3x5nF/uug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=Pi8UCkwgJIEOdVhZWtrj0Uu7QhaUGHxfSoe/0iViBsQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VGv4Nqd69740Vc6yZNkxc5pioaSZFJdhsYvnRsPbFzhdGbH7qTY9KZHIuaBDrIiYgY0PzvB9YSt5LukblcYPQi+X7bij3JRR61vCtTgrsbt5/oNB6cwnUE5xCTykFgCxN7nmsC8DAE9KWt5BR/VZ2Oh/rH7b7R+J2OSAyQz8Hlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SPnF481b; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SPnF481b" Received: by smtp.kernel.org (Postfix) with ESMTPS id 71632C19422; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=Pi8UCkwgJIEOdVhZWtrj0Uu7QhaUGHxfSoe/0iViBsQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SPnF481bRUsR+gspp1H7c7FoBsi2sp1mhFut3RZ+O9XpW8nU8e5495pzHmTi773vQ EtfGr0sKZkekLd3NBU2AT2GTOhHQ6KZRPlWXM2GlGY12ScmJ/mMG2lFNGA+XAnJla7 IHgdnn1eOMWPpUGLkCb+51ZSBowDSejAvKZXL9hLTNrWxTn4xK8znDYVah6Ww2dyFH sjvYXrXmqkK8SwcOG7Caq7hd45dyVNz7tV0vGpYYq5kA3rteyC/LAut0Ku646lB2an uiKSxgcnsuHx/gMxgko7/xMd7cCFMDhkYN9H/0e+iba+/WKzxM/2YxkrQxh0RWvMjh NjzJaJqltNniw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60F55CAC5BB; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:24 +0400 Subject: [PATCH v16 8/9] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-8-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1186; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=KvYbb087e0IlFv5OJiQl0AaX3Z3Wvu4mRV8HcggrQbU=; b=Ah/Gp1IRi9I3RMtMSorPmK/+gcsW3TwS7R/hNSgj/sNzrA7Tu6dkcYzMMxwReGloAXjEVZhP8 mSOlAuQdzujCMwH1mc5aqE8mwyfl1f3od1bKV1NL9p6SYyR3BwOwbI/ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab221c0d99f819294abf63369987da..4ff6e38521ed94fac0f4caac5c5= b0d9be3704d7e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.51.0 From nobody Wed Oct 1 20:32:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A12A7302163; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; cv=none; b=Scs6+MNd92+WqLZdmAUAH9RCldjHfqYQRhWfB2snSJOCX8Q8ExdA+kUJvR1RK4aBxDctw4d63DG+J9zx/PiCFVLTfLbOhuOSE4dLBKv4c6m6VEtM37cuADGQT8DspjB+WdDYXNHhqtj7qOge96G7oBcGp7GLD2+LWSpzm2ravng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759327463; c=relaxed/simple; bh=Qig9iK4nvL5LHyipokVQp0lUQ/1VoYkhR9fI/C/GaXY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=svHS7ORvk0NYfT5ujWTQ38XsBMgEB21hDf1QAyV7PfrvLUGBMcWHSMIohaN7KwsS5uRNPjqTahGqLPrnsqIBpU3+J/mUjdMMWq8FW2Ag5VVOFbDqAO0D9gq/M4b1Ns5rVrb+gU3S+EMAmuWfYRsWbD0RCeBkG4fEEZZ4BS/yalM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XnrKgHR5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XnrKgHR5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7BF30C4CEF9; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759327463; bh=Qig9iK4nvL5LHyipokVQp0lUQ/1VoYkhR9fI/C/GaXY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XnrKgHR5eQymr7fza3qejLHTxW9oSDAigNz1HQrf7C2HSP632slMw68ZjLtZIe7GM Wh0VK0X5CBQ5nZSaVfBTkRhS4Qpljq2q0HtJlguPmEiuYoNMOFmGmEF6qA5NMbO0nV 00j2l44JwGma3q34sN7zN0T3I71xWwKZaRcIhe+uI+8DKRm35j3nISAUvNRCXZ+NRU v0B6cx9M+SSZ4XsLCTqYt4IcAn9EufPhCc1GaBtNgZMGoIqAm1HnnhFowwHELEhqVp FoPuPRRx/7iXuQkI6UxWKhTGZ8CJMs/1lNOdpXvoaDT+61rbiC7s01onkBKEmfj7nB EWvkuV45TVZ6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FF5ACCA472; Wed, 1 Oct 2025 14:04:23 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 01 Oct 2025 18:04:25 +0400 Subject: [PATCH v16 9/9] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251001-ipq-pwm-v16-9-300f237e0e68@outlook.com> References: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> In-Reply-To: <20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759327459; l=1167; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=NmbkhirvZThnPU/pW0My5tw+qkhmpOdG5zYALYy2sl8=; b=mRIJkTBICpo767F3L1D+I4trpkJEfSQhzckcIrKsIyVch0qXnC8vEbY8ImffMEFPEhdwkGJvj b7uFpOYuh81ACkS5gNTziALoCeOHHkvaRvy6ETQivDBfTis+2G88o5X X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 86c9cb9fffc98fdd1b0b08e81428ce5e7bb87e17..8dba80d76d609a317a66f514c64= ab8f5612e6938 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -449,6 +449,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.51.0