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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2025 13:18:02.0456 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 055e468b-ee33-4e98-023a-08de0023c880 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9191 Content-Type: text/plain; charset="utf-8" AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma --- Changes in v4: Configured 8 read and 8 write channels for Xilinx vendor Added checks to validate vendor ID for vendor specific vsec id. Added Xilinx specific vendor id for vsec specific to Xilinx Added the LL and data region offsets, size as input params to function dw_edma_set_chan_region_offset(). Moved the LL and data region offsets assignment to function for Xilinx specific case. Corrected comments. Changes in v3: Corrected a typo when assigning AMD (Xilinx) vsec id macro and condition check. Changes in v2: Reverted the devmem_phys_off type to u64. Renamed the function appropriately to suit the functionality for setting the LL & data region offsets. Changes in v1: Removed the pci device id from pci_ids.h file. Added the vendor id macro as per the suggested method. Changed the type of the newly added devmem_phys_off variable. Added to logic to assign offsets for LL and data region blocks in case more number of channels are enabled than given in amd_mdb_data struct. --- drivers/dma/dw-edma/dw-edma-pcie.c | 130 ++++++++++++++++++++++++++++- 1 file changed, 128 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 3371e0a76d3c..b26a55eec5e4 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -17,12 +17,23 @@ =20 #include "dw-edma-core.h" =20 +/* Synopsys */ #define DW_PCIE_VSEC_DMA_ID 0x6 #define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) =20 +/* AMD MDB (Xilinx) specific defines */ +#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 +#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 +#define PCI_DEVICE_ID_AMD_MDB_B054 0xb054 +#define DW_PCIE_AMD_MDB_INVALID_ADDR (~0ULL) +#define DW_PCIE_XILINX_LL_OFF_GAP 0x200000 +#define DW_PCIE_XILINX_LL_SIZE 0x800 +#define DW_PCIE_XILINX_DT_OFF_GAP 0x100000 +#define DW_PCIE_XILINX_DT_SIZE 0x800 + #define DW_BLOCK(a, b, c) \ { \ .bar =3D a, \ @@ -50,6 +61,7 @@ struct dw_edma_pcie_data { u8 irqs; u16 wr_ch_cnt; u16 rd_ch_cnt; + u64 devmem_phys_off; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -90,6 +102,64 @@ static const struct dw_edma_pcie_data snps_edda_data = =3D { .rd_ch_cnt =3D 2, }; =20 +static const struct dw_edma_pcie_data amd_mdb_data =3D { + /* MDB registers location */ + .rg.bar =3D BAR_0, + .rg.off =3D 0x00001000, /* 4 Kbytes */ + .rg.sz =3D 0x00002000, /* 8 Kbytes */ + + /* Other */ + .mf =3D EDMA_MF_HDMA_NATIVE, + .irqs =3D 1, + .wr_ch_cnt =3D 8, + .rd_ch_cnt =3D 8, +}; + +static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, + enum pci_barno bar, off_t start_off, + off_t ll_off_gap, size_t ll_size, + off_t dt_off_gap, size_t dt_size) +{ + u16 i; + off_t off; + u16 wr_ch =3D pdata->wr_ch_cnt; + u16 rd_ch =3D pdata->rd_ch_cnt; + + off =3D start_off; + + /* Write channel LL region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->ll_wr[i].bar =3D bar; + pdata->ll_wr[i].off =3D off; + pdata->ll_wr[i].sz =3D ll_size; + off +=3D ll_off_gap; + } + + /* Read channel LL region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->ll_rd[i].bar =3D bar; + pdata->ll_rd[i].off =3D off; + pdata->ll_rd[i].sz =3D ll_size; + off +=3D ll_off_gap; + } + + /* Write channel data region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->dt_wr[i].bar =3D bar; + pdata->dt_wr[i].off =3D off; + pdata->dt_wr[i].sz =3D dt_size; + off +=3D dt_off_gap; + } + + /* Read channel data region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->dt_rd[i].bar =3D bar; + pdata->dt_rd[i].off =3D off; + pdata->dt_rd[i].sz =3D dt_size; + off +=3D dt_off_gap; + } +} + static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) { return pci_irq_vector(to_pci_dev(dev), nr); @@ -120,9 +190,24 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, u32 val, map; u16 vsec; u64 off; + int cap; =20 - vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, - DW_PCIE_VSEC_DMA_ID); + /* + * Synopsys and AMD (Xilinx) use the same VSEC ID for the purpose + * of map, channel counts, etc. + */ + switch (pdev->vendor) { + case PCI_VENDOR_ID_SYNOPSYS: + cap =3D DW_PCIE_VSEC_DMA_ID; + break; + case PCI_VENDOR_ID_XILINX: + cap =3D DW_PCIE_XILINX_MDB_VSEC_DMA_ID; + break; + default: + return; + } + + vsec =3D pci_find_vsec_capability(pdev, pdev->vendor, cap); if (!vsec) return; =20 @@ -155,6 +240,24 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, off <<=3D 32; off |=3D val; pdata->rg.off =3D off; + + /* Xilinx specific VSEC capability */ + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, + DW_PCIE_XILINX_MDB_VSEC_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_ID(val) !=3D 0x20 || + PCI_VNDR_HEADER_REV(val) !=3D 0x1) + return; + + pci_read_config_dword(pdev, vsec + 0xc, &val); + off =3D val; + pci_read_config_dword(pdev, vsec + 0x8, &val); + off <<=3D 32; + off |=3D val; + pdata->devmem_phys_off =3D off; } =20 static int dw_edma_pcie_probe(struct pci_dev *pdev, @@ -179,6 +282,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, } =20 memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); + vsec_data->devmem_phys_off =3D DW_PCIE_AMD_MDB_INVALID_ADDR; =20 /* * Tries to find if exists a PCIe Vendor-Specific Extended Capability @@ -186,6 +290,26 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, */ dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data); =20 + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { + /* + * There is no valid address found for the LL memory + * space on the device side. + */ + if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_AMD_MDB_INVALID_ADDR) + return -EINVAL; + + /* + * Configure the channel LL and data blocks if number of + * channels enabled in VSEC capability are more than the + * channels configured in amd_mdb_data. + */ + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, + DW_PCIE_XILINX_LL_OFF_GAP, + DW_PCIE_XILINX_LL_SIZE, + DW_PCIE_XILINX_DT_OFF_GAP, + DW_PCIE_XILINX_DT_SIZE); + } + /* Mapping PCI BAR regions */ mask =3D BIT(vsec_data->rg.bar); for (i =3D 0; i < vsec_data->wr_ch_cnt; i++) { @@ -367,6 +491,8 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev) =20 static const struct pci_device_id dw_edma_pcie_id_table[] =3D { { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_AMD_MDB_B054), + (kernel_ulong_t)&amd_mdb_data }, { } }; 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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN1PEPF0000468D.mail.protection.outlook.com (10.167.243.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.9 via Frontend Transport; Tue, 30 Sep 2025 13:18:05 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 30 Sep 2025 06:18:03 -0700 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 30 Sep 2025 06:18:02 -0700 Received: from xhdapps-pcie2.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 30 Sep 2025 06:18:00 -0700 From: Devendra K Verma To: , , CC: , , , Subject: [RESEND PATCH v4 2/2] dmaengine: dw-edma: Add non-LL mode Date: Tue, 30 Sep 2025 18:47:55 +0530 Message-ID: <20250930131755.3844-3-devendra.verma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250930131755.3844-1-devendra.verma@amd.com> References: <20250930131755.3844-1-devendra.verma@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468D:EE_|IA0PR12MB7531:EE_ X-MS-Office365-Filtering-Correlation-Id: 89eeb0f4-9420-49fe-0f54-08de0023ca59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2025 13:18:05.1448 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89eeb0f4-9420-49fe-0f54-08de0023ca59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7531 Content-Type: text/plain; charset="utf-8" AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - When a valid physical base address is not configured via the Xilinx VSEC capability then the IP can still be used in non-LL mode. The default mode for all the DMA transactions and for all the DMA channels then is non-LL mode. - When a valid physical base address is configured but the client wants to use the non-LL mode for DMA transactions then also the flexibility is provided via the peripheral_config struct member of dma_slave_config. In this case the channels can be individually configured in non-LL mode. This use case is desirable for single DMA transfer of a chunk, this saves the effort of preparing the Link List. Signed-off-by: Devendra K Verma --- Changes in v4 No change Changes in v3 No change Changes in v2 Reverted the function return type to u64 for dw_edma_get_phys_addr(). Changes in v1 Changed the function return type for dw_edma_get_phys_addr(). Corrected the typo raised in review. --- drivers/dma/dw-edma/dw-edma-core.c | 38 +++++++++++++--- drivers/dma/dw-edma/dw-edma-core.h | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 44 +++++++++++++------ drivers/dma/dw-edma/dw-hdma-v0-core.c | 62 ++++++++++++++++++++++++++- include/linux/dma/edma.h | 1 + 5 files changed, 127 insertions(+), 19 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index b43255f914f3..3283ac5ffeeb 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -223,8 +223,28 @@ static int dw_edma_device_config(struct dma_chan *dcha= n, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + int nollp =3D 0; + + if (WARN_ON(config->peripheral_config && + config->peripheral_size !=3D sizeof(int))) + return -EINVAL; =20 memcpy(&chan->config, config, sizeof(*config)); + + /* + * When there is no valid LLP base address available + * then the default DMA ops will use the non-LL mode. + * Cases where LL mode is enabled and client wants + * to use the non-LL mode then also client can do + * so via providing the peripheral_config param. + */ + if (config->peripheral_config) + nollp =3D *(int *)config->peripheral_config; + + chan->nollp =3D false; + if (chan->dw->chip->nollp || (!chan->dw->chip->nollp && nollp)) + chan->nollp =3D true; + chan->configured =3D true; =20 return 0; @@ -353,7 +373,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) struct dw_edma_chan *chan =3D dchan2dw_edma_chan(xfer->dchan); enum dma_transfer_direction dir =3D xfer->direction; struct scatterlist *sg =3D NULL; - struct dw_edma_chunk *chunk; + struct dw_edma_chunk *chunk =3D NULL; struct dw_edma_burst *burst; struct dw_edma_desc *desc; u64 src_addr, dst_addr; @@ -419,9 +439,11 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) if (unlikely(!desc)) goto err_alloc; =20 - chunk =3D dw_edma_alloc_chunk(desc); - if (unlikely(!chunk)) - goto err_alloc; + if (!chan->nollp) { + chunk =3D dw_edma_alloc_chunk(desc); + if (unlikely(!chunk)) + goto err_alloc; + } =20 if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { src_addr =3D xfer->xfer.il->src_start; @@ -450,7 +472,13 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) break; =20 - if (chunk->bursts_alloc =3D=3D chan->ll_max) { + /* + * For non-LL mode, only a single burst can be handled + * in a single chunk unlike LL mode where multiple bursts + * can be configured in a single chunk. + */ + if ((chunk && chunk->bursts_alloc =3D=3D chan->ll_max) || + chan->nollp) { chunk =3D dw_edma_alloc_chunk(desc); if (unlikely(!chunk)) goto err_alloc; diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9e0b15..2a4ad45fbe01 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -86,6 +86,7 @@ struct dw_edma_chan { u8 configured; =20 struct dma_slave_config config; + bool nollp; }; =20 struct dw_edma_irq { diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index b26a55eec5e4..1c4d10c38823 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -260,6 +260,15 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, pdata->devmem_phys_off =3D off; } =20 +static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata, + enum pci_barno bar) +{ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) + return pdata->devmem_phys_off; + return pci_bus_address(pdev, bar); +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -269,6 +278,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; + bool nollp =3D false; =20 vsec_data =3D kmalloc(sizeof(*vsec_data), GFP_KERNEL); if (!vsec_data) @@ -293,21 +303,24 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { /* * There is no valid address found for the LL memory - * space on the device side. + * space on the device side. In the absence of LL base + * address use the non-LL mode or simple mode supported by + * the HDMA IP. */ if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_AMD_MDB_INVALID_ADDR) - return -EINVAL; + nollp =3D true; =20 /* * Configure the channel LL and data blocks if number of * channels enabled in VSEC capability are more than the * channels configured in amd_mdb_data. */ - dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, - DW_PCIE_XILINX_LL_OFF_GAP, - DW_PCIE_XILINX_LL_SIZE, - DW_PCIE_XILINX_DT_OFF_GAP, - DW_PCIE_XILINX_DT_SIZE); + if (!nollp) + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, + DW_PCIE_XILINX_LL_OFF_GAP, + DW_PCIE_XILINX_LL_SIZE, + DW_PCIE_XILINX_DT_OFF_GAP, + DW_PCIE_XILINX_DT_SIZE); } =20 /* Mapping PCI BAR regions */ @@ -355,6 +368,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf =3D vsec_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; + chip->nollp =3D nollp; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; @@ -363,7 +377,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !nollp; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_wr[i]; @@ -374,7 +388,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -383,12 +398,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } =20 - for (i =3D 0; i < chip->ll_rd_cnt; i++) { + for (i =3D 0; i < chip->ll_rd_cnt && !nollp; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_rd[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_rd[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_rd[i]; @@ -399,7 +415,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -408,7 +425,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe909..befb9e0c9bd0 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chun= k *chunk) readl(chunk->ll_region.vaddr.io); } =20 -static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool fir= st) { struct dw_edma_chan *chan =3D chunk->chan; struct dw_edma *dw =3D chan->dw; @@ -263,6 +263,66 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk= *chunk, bool first) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } =20 +static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk) +{ + struct dw_edma_chan *chan =3D chunk->chan; + struct dw_edma *dw =3D chan->dw; + struct dw_edma_burst *child; + u32 val; + + list_for_each_entry(child, &chunk->burst->list, list) { + SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0)); + + /* Source address */ + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, + lower_32_bits(child->sar)); + SET_CH_32(dw, chan->dir, chan->id, sar.msb, + upper_32_bits(child->sar)); + + /* Destination address */ + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, + lower_32_bits(child->dar)); + SET_CH_32(dw, chan->dir, chan->id, dar.msb, + upper_32_bits(child->dar)); + + /* Transfer size */ + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); + + /* Interrupt setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | + HDMA_V0_STOP_INT_MASK | + HDMA_V0_ABORT_INT_MASK | + HDMA_V0_LOCAL_STOP_INT_EN | + HDMA_V0_LOCAL_ABORT_INT_EN; + + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) { + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_REMOTE_ABORT_INT_EN; + } + + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); + + /* Channel control setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, control1); + val &=3D ~HDMA_V0_LINKLIST_EN; + SET_CH_32(dw, chan->dir, chan->id, control1, val); + + /* Ring the doorbell */ + SET_CH_32(dw, chan->dir, chan->id, doorbell, + HDMA_V0_DOORBELL_START); + } +} + +static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +{ + struct dw_edma_chan *chan =3D chunk->chan; + + if (!chan->nollp) + dw_hdma_v0_core_ll_start(chunk, first); + else + dw_hdma_v0_core_non_ll_start(chunk); +} + static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw =3D chan->dw; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747689f6..e14e16f4cc79 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -99,6 +99,7 @@ struct dw_edma_chip { enum dw_edma_map_format mf; =20 struct dw_edma *dw; + bool nollp; }; =20 /* Export to the platform drivers */ --=20 2.43.0