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charset="utf-8" Initialise the GSP resource manager arguments (rmargs) which provide initialisation parameters to the GSP firmware during boot. The rmargs structure contains arguments to configure the GSP message/command queue location. These are mapped for coherent DMA and added to the libos data structure for access when booting GSP. Signed-off-by: Alistair Popple --- Changes for v2: - Rebased on Alex's latest series --- drivers/gpu/nova-core/gsp.rs | 16 +++++ drivers/gpu/nova-core/gsp/cmdq.rs | 24 +++++++- drivers/gpu/nova-core/gsp/fw.rs | 60 +++++++++++++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 33 ++++++++++ 4 files changed, 130 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 3132f1009897..9e5dd9e5a316 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -3,6 +3,7 @@ mod boot; mod fw; =20 +use fw::GspArgumentsCached; pub(crate) use fw::{GspFwWprMeta, LibosParams}; =20 use kernel::alloc::flags::GFP_KERNEL; @@ -37,6 +38,7 @@ pub(crate) struct Gsp { pub logintr: CoherentAllocation, pub logrm: CoherentAllocation, pub cmdq: Cmdq, + rmargs: CoherentAllocation, } =20 #[repr(C)] @@ -93,12 +95,26 @@ pub(crate) fn new(pdev: &pci::Device) ->= Result::alloc_coh= erent( + dev, + 1, + GFP_KERNEL | __GFP_ZERO, + )?; + dma_write!(libos[3] =3D LibosMemoryRegionInitArgument::new("RMARGS= ", &rmargs))?; + + dma_write!( + rmargs[0] =3D fw::GspArgumentsCached::new( + fw::MessageQueueInitArguments::new(&cmdq), + fw::GspSrInitArguments::new() + ) + )?; =20 Ok(try_pin_init!(Self { libos, loginit, logintr, logrm, + rmargs, cmdq, })) } diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/= cmdq.rs index 7d43dc987ba2..2fd6b31db9e9 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -6,7 +6,7 @@ =20 use kernel::alloc::flags::GFP_KERNEL; use kernel::device; -use kernel::dma::CoherentAllocation; +use kernel::dma::{CoherentAllocation, DmaAddress}; use kernel::dma_write; use kernel::prelude::*; use kernel::sync::aref::ARef; @@ -202,10 +202,25 @@ pub(crate) struct Cmdq { dev: ARef, seq: u32, gsp_mem: DmaGspMem, - pub _nr_ptes: u32, } =20 impl Cmdq { + /// Offset of the data after the PTEs. + const POST_PTE_OFFSET: usize =3D core::mem::offset_of!(GspMem, cpuq); + + /// Offset of command queue ring buffer. + pub(crate) const CMDQ_OFFSET: usize =3D core::mem::offset_of!(GspMem, = cpuq) + + core::mem::offset_of!(Msgq, msgq) + - Self::POST_PTE_OFFSET; + + /// Offset of message queue ring buffer. + pub(crate) const STATQ_OFFSET: usize =3D core::mem::offset_of!(GspMem,= gspq) + + core::mem::offset_of!(Msgq, msgq) + - Self::POST_PTE_OFFSET; + + /// Number of page table entries for the GSP shared region. + pub(crate) const NUM_PTES: usize =3D size_of::() >> GSP_PAGE_S= HIFT; + pub(crate) fn new(dev: &device::Device) -> Result= { let gsp_mem =3D DmaGspMem::new(dev)?; let nr_ptes =3D size_of::() >> GSP_PAGE_SHIFT; @@ -215,7 +230,6 @@ pub(crate) fn new(dev: &device::Device) = -> Result { dev: dev.into(), seq: 0, gsp_mem, - _nr_ptes: nr_ptes as u32, }) } =20 @@ -399,4 +413,8 @@ pub(crate) fn receive_msg_from_gsp( .advance_cpu_read_ptr(msg_header.length().div_ceil(GSP_PAGE_SI= ZE as u32)); result } + + pub(crate) fn dma_handle(&self) -> DmaAddress { + self.gsp_mem.0.dma_handle() + } } diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index ee86abe7ea10..aec0db50adea 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -17,6 +17,7 @@ use crate::firmware::gsp::GspFirmware; use crate::gpu::Chipset; use crate::gsp; +use crate::gsp::cmdq::Cmdq; use crate::gsp::FbLayout; use crate::gsp::GSP_PAGE_SIZE; =20 @@ -453,3 +454,62 @@ unsafe impl AsBytes for GspMsgElement {} // SAFETY: This struct only contains integer types for which all bit patte= rns // are valid. unsafe impl FromBytes for GspMsgElement {} + +#[repr(transparent)] +pub(crate) struct GspArgumentsCached(bindings::GSP_ARGUMENTS_CACHED); + +impl GspArgumentsCached { + pub(crate) fn new( + queue_arguments: MessageQueueInitArguments, + sr_arguments: GspSrInitArguments, + ) -> Self { + Self(bindings::GSP_ARGUMENTS_CACHED { + messageQueueInitArguments: queue_arguments.0, + srInitArguments: sr_arguments.0, + bDmemStack: 1, + ..Default::default() + }) + } +} + +impl From for bindings::GSP_ARGUMENTS_CACHED { + fn from(value: GspArgumentsCached) -> Self { + value.0 + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspArgumentsCached {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspArgumentsCached {} + +#[repr(transparent)] +pub(crate) struct MessageQueueInitArguments(bindings::MESSAGE_QUEUE_INIT_A= RGUMENTS); + +impl MessageQueueInitArguments { + pub(crate) fn new(cmdq: &Cmdq) -> Self { + Self(bindings::MESSAGE_QUEUE_INIT_ARGUMENTS { + sharedMemPhysAddr: cmdq.dma_handle(), + pageTableEntryCount: Cmdq::NUM_PTES as u32, + cmdQueueOffset: Cmdq::CMDQ_OFFSET as u64, + statQueueOffset: Cmdq::STATQ_OFFSET as u64, + ..Default::default() + }) + } +} + +#[repr(transparent)] +pub(crate) struct GspSrInitArguments(bindings::GSP_SR_INIT_ARGUMENTS); + +impl GspSrInitArguments { + pub(crate) fn new() -> Self { + Self(bindings::GSP_SR_INIT_ARGUMENTS { + oldLevel: 0, + flags: 0, + bInPMTransition: 0, + ..Default::default() + }) + } +} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 3d96d91e5b12..b87c4e6cb857 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -319,6 +319,39 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) ->= ::core::fmt::Result { pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 =3D 4131; pub type _bindgen_ty_3 =3D ffi::c_uint; #[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct MESSAGE_QUEUE_INIT_ARGUMENTS { + pub sharedMemPhysAddr: u64_, + pub pageTableEntryCount: u32_, + pub __bindgen_padding_0: [u8; 4usize], + pub cmdQueueOffset: u64_, + pub statQueueOffset: u64_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GSP_SR_INIT_ARGUMENTS { + pub oldLevel: u32_, + pub flags: u32_, + pub bInPMTransition: u8_, + pub __bindgen_padding_0: [u8; 3usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GSP_ARGUMENTS_CACHED { + pub messageQueueInitArguments: MESSAGE_QUEUE_INIT_ARGUMENTS, + pub srInitArguments: GSP_SR_INIT_ARGUMENTS, + pub gpuInstance: u32_, + pub bDmemStack: u8_, + pub __bindgen_padding_0: [u8; 7usize], + pub profilerArgs: GSP_ARGUMENTS_CACHED__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GSP_ARGUMENTS_CACHED__bindgen_ty_1 { + pub pa: u64_, + pub size: u64_, +} +#[repr(C)] #[derive(Copy, Clone)] pub union rpc_message_rpc_union_field_v03_00 { pub spare: u32_, --=20 2.50.1