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charset="utf-8" Boot the GSP to the RISC-V active state. Completing the boot requires running the CPU sequencer which will be added in a future commit. Signed-off-by: Alistair Popple Reviewed-by: Lyude Paul --- Changes for v3: - Fixed minor nit from John - Added booter load error thanks to Timur's suggestion Changes for v2: - Rebased on Alex's latest tree --- drivers/gpu/nova-core/falcon.rs | 2 - drivers/gpu/nova-core/firmware/riscv.rs | 3 +- drivers/gpu/nova-core/gsp.rs | 2 +- drivers/gpu/nova-core/gsp/boot.rs | 64 ++++++++++++++++++++++++- 4 files changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 0cb7821341ed..960801f74bf1 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -614,14 +614,12 @@ pub(crate) fn signature_reg_fuse_version( /// Check if the RISC-V core is active. /// /// Returns `true` if the RISC-V core is active, `false` otherwise. - #[expect(unused)] pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result { let cpuctl =3D regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); Ok(cpuctl.active_stat()) } =20 /// Write the application version to the OS register. - #[expect(dead_code)] pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) ->= Result<()> { regs::NV_PFALCON_FALCON_OS::default() .set_value(app_version) diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs index dec33d2b631a..d1a9e027bac3 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -50,7 +50,6 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result { } =20 /// A parsed firmware for a RISC-V core, ready to be loaded and run. -#[expect(unused)] pub(crate) struct RiscvFirmware { /// Offset at which the code starts in the firmware image. pub code_offset: u32, @@ -59,7 +58,7 @@ pub(crate) struct RiscvFirmware { /// Offset at which the manifest starts in the firmware image. pub manifest_offset: u32, /// Application version. - app_version: u32, + pub app_version: u32, /// Device-mapped firmware image. pub ucode: DmaObject, } diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 1d5544d9dfb4..d5a33fbf8fb6 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -34,7 +34,7 @@ /// GSP runtime data. #[pin_data] pub(crate) struct Gsp { - libos: CoherentAllocation, + pub libos: CoherentAllocation, pub loginit: CoherentAllocation, pub logintr: CoherentAllocation, pub logrm: CoherentAllocation, diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 0b306313ec53..77e9adf80f20 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -5,6 +5,7 @@ use kernel::dma_write; use kernel::pci; use kernel::prelude::*; +use kernel::time::Delta; =20 use crate::driver::Bar0; use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; @@ -19,6 +20,7 @@ use crate::gsp::commands::{build_registry, set_system_info}; use crate::gsp::GspFwWprMeta; use crate::regs; +use crate::util; use crate::vbios::Vbios; =20 impl super::Gsp { @@ -127,7 +129,7 @@ pub(crate) fn boot( =20 Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?; =20 - let _booter_loader =3D BooterFirmware::new( + let booter_loader =3D BooterFirmware::new( dev, BooterKind::Loader, chipset, @@ -143,6 +145,66 @@ pub(crate) fn boot( set_system_info(&mut self.cmdq, pdev, bar)?; build_registry(&mut self.cmdq, bar)?; =20 + gsp_falcon.reset(bar)?; + let libos_handle =3D self.libos.dma_handle(); + let (mbox0, mbox1) =3D gsp_falcon.boot( + bar, + Some(libos_handle as u32), + Some((libos_handle >> 32) as u32), + )?; + dev_dbg!( + pdev.as_ref(), + "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", + mbox0, + mbox1 + ); + + dev_dbg!( + pdev.as_ref(), + "Using SEC2 to load and run the booter_load firmware...\n" + ); + + sec2_falcon.reset(bar)?; + sec2_falcon.dma_load(bar, &booter_loader)?; + let wpr_handle =3D wpr_meta.dma_handle(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + bar, + Some(wpr_handle as u32), + Some((wpr_handle >> 32) as u32), + )?; + dev_dbg!( + pdev.as_ref(), + "SEC2 MBOX0: {:#x}, MBOX1{:#x}\n", + mbox0, + mbox1 + ); + + if mbox0 !=3D 0 { + dev_err!( + pdev.as_ref(), + "Booter-load failed with error {:#x}\n", + mbox0 + ); + return Err(ENODEV); + } + + gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version)?; + + // Poll for RISC-V to become active before running sequencer + util::wait_on(Delta::from_secs(5), || { + if gsp_falcon.is_riscv_active(bar).unwrap_or(false) { + Some(()) + } else { + None + } + })?; + + dev_dbg!( + pdev.as_ref(), + "RISC-V active? {}\n", + gsp_falcon.is_riscv_active(bar)?, + ); + Ok(()) } } --=20 2.50.1