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charset="utf-8" Set the correct DMA mask. Without this DMA will fail on some setups. Signed-off-by: Alistair Popple --- Changes for v2: - Update DMA mask to correct value for Ampere/Turing (47 bits) --- drivers/gpu/nova-core/driver.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 1380b47617f7..ccc97340206e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::{auxiliary, bindings, c_str, device::Core, pci, prelude::*, si= zes::SZ_16M, sync::Arc}; +use kernel::{ + auxiliary, bindings, c_str, device::Core, dma::Device, dma::DmaMask, p= ci, prelude::*, + sizes::SZ_16M, sync::Arc, +}; =20 use crate::gpu::Gpu; =20 @@ -34,6 +37,9 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo) = -> Result())? }; + let devres_bar =3D Arc::pin_init( pdev.iomap_region_sized::(0, c_str!("nova-core/bar0= ")), GFP_KERNEL, --=20 2.50.1 From nobody Thu Oct 2 05:06:28 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011022.outbound.protection.outlook.com [40.93.194.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8834304BBC; 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charset="utf-8" The GSP requires several areas of memory to operate. Each of these have their own simple embedded page tables. Set these up and map them for DMA to/from GSP using CoherentAllocation's. Return the DMA handle describing where each of these regions are for future use when booting GSP. Signed-off-by: Alistair Popple --- Change for v3: - Clean up the PTE array creation, with much thanks to Alex for doing most it (please let me know if I should put you as co-developer!) Changes for v2: - Renamed GspMemOjbects to Gsp as that is what they are - Rebased on Alex's latest series --- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/gsp.rs | 83 +++++++++++++++++-- drivers/gpu/nova-core/gsp/fw.rs | 39 +++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 19 +++++ 4 files changed, 134 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 5da9ad726483..c939b3868271 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -221,7 +221,7 @@ pub(crate) fn new<'a>( =20 sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset, bar, tru= e)?, =20 - gsp <- Gsp::new(), + gsp <- Gsp::new(pdev)?, =20 _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, =20 diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 503ce8ee0420..91aa9ce17c57 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -1,27 +1,94 @@ // SPDX-License-Identifier: GPL-2.0 =20 mod boot; - -use kernel::prelude::*; - mod fw; =20 pub(crate) use fw::{GspFwWprMeta, LibosParams}; =20 +use kernel::device; +use kernel::dma::CoherentAllocation; +use kernel::dma::DmaAddress; +use kernel::dma_write; +use kernel::pci; +use kernel::prelude::*; use kernel::ptr::Alignment; +use kernel::transmute::AsBytes; + +use fw::LibosMemoryRegionInitArgument; =20 pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; pub(crate) const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new::<{ 1 <<= 20 }>(); =20 +/// Number of GSP pages to use in a RM log buffer. +const RM_LOG_BUFFER_NUM_PAGES: usize =3D 0x10; + /// GSP runtime data. -/// -/// This is an empty pinned placeholder for now. #[pin_data] -pub(crate) struct Gsp {} +pub(crate) struct Gsp { + libos: CoherentAllocation, + pub loginit: CoherentAllocation, + pub logintr: CoherentAllocation, + pub logrm: CoherentAllocation, +} + +#[repr(C)] +struct PteArray([u64; NUM_ENTRIES]); +/// SAFETY: arrays of `u64` implement `AsBytes` and we are but a wrapper a= round it. +unsafe impl AsBytes for PteArray {} +impl PteArray { + fn new(handle: DmaAddress) -> Self { + let mut ptes =3D [0u64; NUM_PAGES]; + for (i, pte) in ptes.iter_mut().enumerate() { + *pte =3D handle + ((i as u64) << GSP_PAGE_SHIFT); + } + + Self(ptes) + } +} + +/// Creates a new `CoherentAllocation` with `name` of `size` elements, = and +/// register it into the `libos` object at argument position `libos_arg_nr= `. +fn create_logbuffer_dma_object( + dev: &device::Device, +) -> Result> { + let mut obj =3D CoherentAllocation::::alloc_coherent( + dev, + RM_LOG_BUFFER_NUM_PAGES * GSP_PAGE_SIZE, + GFP_KERNEL | __GFP_ZERO, + )?; + let ptes =3D PteArray::::new(obj.dma_handle()= ); + + // SAFETY: `obj` has just been created and we are its sole user. + unsafe { + // Copy the self-mapping PTE at the expected location. + obj.as_slice_mut(size_of::(), size_of_val(&ptes))? + .copy_from_slice(ptes.as_bytes()) + }; + + Ok(obj) +} =20 impl Gsp { - pub(crate) fn new() -> impl PinInit { - pin_init!(Self {}) + pub(crate) fn new(pdev: &pci::Device) -> Result> { + let dev =3D pdev.as_ref(); + let libos =3D CoherentAllocation:::= :alloc_coherent( + dev, + GSP_PAGE_SIZE / size_of::(), + GFP_KERNEL | __GFP_ZERO, + )?; + let loginit =3D create_logbuffer_dma_object(dev)?; + dma_write!(libos[0] =3D LibosMemoryRegionInitArgument::new("LOGINI= T", &loginit))?; + let logintr =3D create_logbuffer_dma_object(dev)?; + dma_write!(libos[1] =3D LibosMemoryRegionInitArgument::new("LOGINT= R", &logintr))?; + let logrm =3D create_logbuffer_dma_object(dev)?; + dma_write!(libos[2] =3D LibosMemoryRegionInitArgument::new("LOGRM"= , &logrm))?; + + Ok(try_pin_init!(Self { + libos, + loginit, + logintr, + logrm, + })) } } diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 181baa401770..dd1e7fc85d85 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -7,8 +7,10 @@ =20 use core::ops::Range; =20 +use kernel::dma::CoherentAllocation; use kernel::ptr::Alignable; use kernel::sizes::SZ_1M; +use kernel::transmute::{AsBytes, FromBytes}; =20 use crate::gpu::Chipset; use crate::gsp; @@ -99,3 +101,40 @@ pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb= _size: u64) -> u64 { /// addresses of the GSP bootloader and firmware. #[repr(transparent)] pub(crate) struct GspFwWprMeta(bindings::GspFwWprMeta); + +#[repr(transparent)] +pub(crate) struct LibosMemoryRegionInitArgument(bindings::LibosMemoryRegio= nInitArgument); + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for LibosMemoryRegionInitArgument {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for LibosMemoryRegionInitArgument {} + +impl LibosMemoryRegionInitArgument { + pub(crate) fn new( + name: &'static str, + obj: &CoherentAllocation, + ) -> Self { + /// Generates the `ID8` identifier required for some GSP objects. + fn id8(name: &str) -> u64 { + let mut bytes =3D [0u8; core::mem::size_of::()]; + + for (c, b) in name.bytes().rev().zip(&mut bytes) { + *b =3D c; + } + + u64::from_ne_bytes(bytes) + } + + Self(bindings::LibosMemoryRegionInitArgument { + id8: id8(name), + pa: obj.dma_handle(), + size: obj.size() as u64, + kind: bindings::LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONT= IGUOUS as u8, + loc: bindings::LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_SY= SMEM as u8, + ..Default::default() + }) + } +} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 0407000cca22..6a14cc324391 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -124,3 +124,22 @@ fn default() -> Self { } } } +pub type LibosAddress =3D u64_; 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charset="utf-8" The GSP requires some pieces of metadata to boot. These are passed in a struct which the GSP transfers via DMA. Create this struct and get a handle to it for future use when booting the GSP. Signed-off-by: Alistair Popple --- Changes for v3: - Don't re-export WPR constants (thanks Alex) Changes for v2: - Rebased on Alex's latest version --- drivers/gpu/nova-core/fb.rs | 1 - drivers/gpu/nova-core/firmware/gsp.rs | 3 +- drivers/gpu/nova-core/firmware/riscv.rs | 6 +- drivers/gpu/nova-core/gsp.rs | 1 + drivers/gpu/nova-core/gsp/boot.rs | 7 +++ drivers/gpu/nova-core/gsp/fw.rs | 57 ++++++++++++++++++- .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 2 + 7 files changed, 69 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 4d6a1f452183..5580498ba2fb 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -87,7 +87,6 @@ pub(crate) fn unregister(&self, bar: &Bar0) { /// /// Contains ranges of GPU memory reserved for a given purpose during the = GSP boot process. #[derive(Debug)] -#[expect(dead_code)] pub(crate) struct FbLayout { /// Range of the framebuffer. Starts at `0`. pub(crate) fb: Range, diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index 9654810834d9..67b85e1db27d 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -127,7 +127,7 @@ pub(crate) struct GspFirmware { /// Size in bytes of the firmware contained in [`Self::fw`]. pub size: usize, /// Device-mapped GSP signatures matching the GPU's [`Chipset`]. - signatures: DmaObject, + pub signatures: DmaObject, /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. pub bootloader: RiscvFirmware, } @@ -212,7 +212,6 @@ pub(crate) fn new<'a, 'b>( })) } =20 - #[expect(unused)] /// Returns the DMA handle of the radix3 level 0 page table. pub(crate) fn radix3_dma_handle(&self) -> DmaAddress { self.level0.dma_handle() diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs index b90acfc81e78..dec33d2b631a 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -53,11 +53,11 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result { #[expect(unused)] pub(crate) struct RiscvFirmware { /// Offset at which the code starts in the firmware image. - code_offset: u32, + pub code_offset: u32, /// Offset at which the data starts in the firmware image. - data_offset: u32, + pub data_offset: u32, /// Offset at which the manifest starts in the firmware image. - manifest_offset: u32, + pub manifest_offset: u32, /// Application version. app_version: u32, /// Device-mapped firmware image. diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 91aa9ce17c57..537a226f98d0 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -14,6 +14,7 @@ use kernel::ptr::Alignment; use kernel::transmute::AsBytes; =20 +use crate::fb::FbLayout; use fw::LibosMemoryRegionInitArgument; =20 pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index fb22508128c4..1d2448331d7a 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 =20 use kernel::device; +use kernel::dma::CoherentAllocation; +use kernel::dma_write; use kernel::pci; use kernel::prelude::*; =20 @@ -14,6 +16,7 @@ FIRMWARE_VERSION, }; use crate::gpu::Chipset; +use crate::gsp::GspFwWprMeta; use crate::regs; use crate::vbios::Vbios; =20 @@ -132,6 +135,10 @@ pub(crate) fn boot( bar, )?; =20 + let wpr_meta =3D + CoherentAllocation::::alloc_coherent(dev, 1, GFP= _KERNEL | __GFP_ZERO)?; + dma_write!(wpr_meta[0] =3D GspFwWprMeta::new(&gsp_fw, &fb_layout))= ?; + Ok(()) } } diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index dd1e7fc85d85..68a7059bc965 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -8,12 +8,14 @@ use core::ops::Range; =20 use kernel::dma::CoherentAllocation; -use kernel::ptr::Alignable; -use kernel::sizes::SZ_1M; +use kernel::ptr::{Alignable, Alignment}; +use kernel::sizes::{SZ_128K, SZ_1M}; use kernel::transmute::{AsBytes, FromBytes}; =20 +use crate::firmware::gsp::GspFirmware; use crate::gpu::Chipset; use crate::gsp; +use crate::gsp::FbLayout; =20 /// Dummy type to group methods related to heap parameters for running the= GSP firmware. pub(crate) struct GspFwHeapParams(()); @@ -102,6 +104,57 @@ pub(crate) fn wpr_heap_size(&self, chipset: Chipset, f= b_size: u64) -> u64 { #[repr(transparent)] pub(crate) struct GspFwWprMeta(bindings::GspFwWprMeta); =20 +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspFwWprMeta {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspFwWprMeta {} + +type GspFwWprMetaBootResumeInfo =3D r570_144::GspFwWprMeta__bindgen_ty_1; +type GspFwWprMetaBootInfo =3D r570_144::GspFwWprMeta__bindgen_ty_1__bindge= n_ty_1; + +impl GspFwWprMeta { + pub(crate) fn new(gsp_firmware: &GspFirmware, fb_layout: &FbLayout) ->= Self { + Self(bindings::GspFwWprMeta { + magic: r570_144::GSP_FW_WPR_META_MAGIC as u64, + revision: u64::from(r570_144::GSP_FW_WPR_META_REVISION), + sysmemAddrOfRadix3Elf: gsp_firmware.radix3_dma_handle(), + sizeOfRadix3Elf: gsp_firmware.size as u64, + sysmemAddrOfBootloader: gsp_firmware.bootloader.ucode.dma_hand= le(), + sizeOfBootloader: gsp_firmware.bootloader.ucode.size() as u64, + bootloaderCodeOffset: u64::from(gsp_firmware.bootloader.code_o= ffset), + bootloaderDataOffset: u64::from(gsp_firmware.bootloader.data_o= ffset), + bootloaderManifestOffset: u64::from(gsp_firmware.bootloader.ma= nifest_offset), + __bindgen_anon_1: GspFwWprMetaBootResumeInfo { + __bindgen_anon_1: GspFwWprMetaBootInfo { + sysmemAddrOfSignature: gsp_firmware.signatures.dma_han= dle(), + sizeOfSignature: gsp_firmware.signatures.size() as u64, + }, + }, + gspFwRsvdStart: fb_layout.heap.start, + nonWprHeapOffset: fb_layout.heap.start, + nonWprHeapSize: fb_layout.heap.end - fb_layout.heap.start, + gspFwWprStart: fb_layout.wpr2.start, + gspFwHeapOffset: fb_layout.wpr2_heap.start, + gspFwHeapSize: fb_layout.wpr2_heap.end - fb_layout.wpr2_heap.s= tart, + gspFwOffset: fb_layout.elf.start, + bootBinOffset: fb_layout.boot.start, + frtsOffset: fb_layout.frts.start, + frtsSize: fb_layout.frts.end - fb_layout.frts.start, + gspFwWprEnd: fb_layout + .vga_workspace + .start + .align_down(Alignment::new::()), + gspFwHeapVfPartitionCount: fb_layout.vf_partition_count, + fbSize: fb_layout.fb.end - fb_layout.fb.start, + vgaWorkspaceOffset: fb_layout.vga_workspace.start, + vgaWorkspaceSize: fb_layout.vga_workspace.end - fb_layout.vga_= workspace.start, + ..Default::default() + }) + } +} + #[repr(transparent)] pub(crate) struct LibosMemoryRegionInitArgument(bindings::LibosMemoryRegio= nInitArgument); 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charset="utf-8" From: Joel Fernandes A data structure that can be used to write across multiple slices which may be out of order in memory. This lets SBuffer user correctly and safely write out of memory order, without error-prone tracking of pointers/offsets. let mut buf1 =3D [0u8; 3]; let mut buf2 =3D [0u8; 5]; let mut sbuffer =3D SBuffer::new([&mut buf1[..], &mut buf2[..]]); let data =3D b"hello"; let result =3D sbuffer.write(data); An internal conversion of gsp.rs to use this resulted in a nice -ve delta: gsp.rs: 37 insertions(+), 99 deletions(-) Co-developed-by: Alistair Popple Signed-off-by: Alistair Popple Signed-off-by: Joel Fernandes Reviewed-by: Lyude Paul --- Changes for v3: - Addressed minor review comment from Lyude --- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/sbuffer.rs | 191 +++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 drivers/gpu/nova-core/sbuffer.rs diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index fffcaee2249f..a6feeba6254c 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -11,6 +11,7 @@ mod gpu; mod gsp; mod regs; +mod sbuffer; mod util; mod vbios; =20 diff --git a/drivers/gpu/nova-core/sbuffer.rs b/drivers/gpu/nova-core/sbuff= er.rs new file mode 100644 index 000000000000..e82f9d97ad21 --- /dev/null +++ b/drivers/gpu/nova-core/sbuffer.rs @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0 + +use core::ops::Deref; + +use kernel::alloc::KVec; +use kernel::error::code::*; +use kernel::prelude::*; + +/// A buffer abstraction for discontiguous byte slices. +/// +/// This allows you to treat multiple non-contiguous `&mut [u8]` slices +/// as a single stream-like read/write buffer. +/// +/// Example: +/// +/// let mut buf1 =3D [0u8; 3]; +/// let mut buf2 =3D [0u8; 5]; +/// let mut sbuffer =3D SWriteBuffer::new([&buf1, &buf2]); +/// +/// let data =3D b"hellowo"; +/// let result =3D sbuffer.write_all(0, data); +/// +/// A sliding window of slices to proceed. +/// +/// Both read and write buffers are implemented in terms of operating on s= lices of a requested +/// size. This base class implements logic that can be shared between the = two to support that. +/// +/// `S` is a slice type, `I` is an iterator yielding `S`. +pub(crate) struct SBuffer { + /// `Some` if we are not at the end of the data yet. + cur_slice: Option, + /// All the slices remaining after `cur_slice`. + slices: I, +} + +impl<'a, I> SBuffer +where + I: Iterator, +{ + #[expect(unused)] + pub(crate) fn new_reader(slices: impl IntoIterator) ->= Self + where + I: Iterator, + { + Self::new(slices) + } + + #[expect(unused)] + pub(crate) fn new_writer(slices: impl IntoIterator) ->= Self + where + I: Iterator, + { + Self::new(slices) + } + + fn new(slices: impl IntoIterator) -> Self + where + I::Item: Deref, + { + let mut slices =3D slices.into_iter(); + + Self { + // Skip empty slices to avoid trouble down the road. + cur_slice: slices.find(|s| !s.deref().is_empty()), + slices, + } + } + + fn get_slice_internal( + &mut self, + len: usize, + mut f: impl FnMut(I::Item, usize) -> (I::Item, I::Item), + ) -> Option + where + I::Item: Deref, + { + match self.cur_slice.take() { + None =3D> None, + Some(cur_slice) =3D> { + if len >=3D cur_slice.len() { + // Caller requested more data than is in the current s= lice, return it entirely + // and prepare the following slice for being used. Ski= p empty slices to avoid + // trouble. + self.cur_slice =3D self.slices.find(|s| !s.is_empty()); + + Some(cur_slice) + } else { + // The current slice can satisfy the request, split it= and return a slice of + // the requested size. + let (ret, next) =3D f(cur_slice, len); + self.cur_slice =3D Some(next); + + Some(ret) + } + } + } + } +} + +/// Provides a way to get non-mutable slices of data to read from. +impl<'a, I> SBuffer +where + I: Iterator, +{ + /// Returns a slice of at most `len` bytes, or `None` if we are at the= end of the data. + /// + /// If a slice shorter than `len` bytes has been returned, the caller = can call this method + /// again until it returns `None` to try and obtain the remainder of t= he data. + fn get_slice(&mut self, len: usize) -> Option<&'a [u8]> { + self.get_slice_internal(len, |s, pos| s.split_at(pos)) + } + + /// Ideally we would implement `Read`, but it is not available in `cor= e`. + /// So mimic `std::io::Read::read_exact`. + #[expect(unused)] + pub(crate) fn read_exact(&mut self, mut dst: &mut [u8]) -> Result { + while !dst.is_empty() { + match self.get_slice(dst.len()) { + None =3D> return Err(ETOOSMALL), + Some(src) =3D> { + let dst_slice; + (dst_slice, dst) =3D dst.split_at_mut(src.len()); + dst_slice.copy_from_slice(src); + } + } + } + + Ok(()) + } + + /// Read all the remaining data into a `KVec`. + /// + /// `self` will be empty after this operation. + #[expect(unused)] + pub(crate) fn read_into_kvec(&mut self, flags: kernel::alloc::Flags) -= > Result> { + let mut buf =3D KVec::::new(); + + if let Some(slice) =3D core::mem::take(&mut self.cur_slice) { + buf.extend_from_slice(slice, flags)?; + } + for slice in &mut self.slices { + buf.extend_from_slice(slice, flags)?; + } + + Ok(buf) + } +} + +/// Provides a way to get mutable slices of data to write into. +impl<'a, I> SBuffer +where + I: Iterator, +{ + /// Returns a mutable slice of at most `len` bytes, or `None` if we ar= e at the end of the data. + /// + /// If a slice shorter than `len` bytes has been returned, the caller = can call this method + /// again until it returns `None` to try and obtain the remainder of t= he data. + fn get_slice_mut(&mut self, len: usize) -> Option<&'a mut [u8]> { + self.get_slice_internal(len, |s, pos| s.split_at_mut(pos)) + } + + /// Ideally we would implement `Write`, but it is not available in `co= re`. + /// So mimic `std::io::Write::write_all`. + #[expect(unused)] + pub(crate) fn write_all(&mut self, mut src: &[u8]) -> Result { + while !src.is_empty() { + match self.get_slice_mut(src.len()) { + None =3D> return Err(ETOOSMALL), + Some(dst) =3D> { + let src_slice; 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charset="utf-8" Add bindings and accessors used for the GSP command queue. Signed-off-by: Alistair Popple --- Changes for v3: - New for v3 --- drivers/gpu/nova-core/gsp/fw.rs | 262 ++++++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 374 ++++++++++++++++++ 2 files changed, 636 insertions(+) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 68a7059bc965..ee86abe7ea10 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -5,9 +5,11 @@ // Alias to avoid repeating the version number with every use. use r570_144 as bindings; =20 +use core::fmt; use core::ops::Range; =20 use kernel::dma::CoherentAllocation; +use kernel::prelude::*; use kernel::ptr::{Alignable, Alignment}; use kernel::sizes::{SZ_128K, SZ_1M}; use kernel::transmute::{AsBytes, FromBytes}; @@ -16,6 +18,7 @@ use crate::gpu::Chipset; use crate::gsp; use crate::gsp::FbLayout; +use crate::gsp::GSP_PAGE_SIZE; =20 /// Dummy type to group methods related to heap parameters for running the= GSP firmware. pub(crate) struct GspFwHeapParams(()); @@ -155,6 +158,120 @@ pub(crate) fn new(gsp_firmware: &GspFirmware, fb_layo= ut: &FbLayout) -> Self { } } =20 +#[derive(PartialEq)] +pub(crate) enum MsgFunction { + // Common function codes + Nop =3D bindings::NV_VGPU_MSG_FUNCTION_NOP as isize, + SetGuestSystemInfo =3D bindings::NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM= _INFO as isize, + AllocRoot =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_ROOT as isize, + AllocDevice =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE as isize, + AllocMemory =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY as isize, + AllocCtxDma =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA as isize, + AllocChannelDma =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA a= s isize, + MapMemory =3D bindings::NV_VGPU_MSG_FUNCTION_MAP_MEMORY as isize, + BindCtxDma =3D bindings::NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA as isize, + AllocObject =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT as isize, + Free =3D bindings::NV_VGPU_MSG_FUNCTION_FREE as isize, + Log =3D bindings::NV_VGPU_MSG_FUNCTION_LOG as isize, + GetGspStaticInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INF= O as isize, + SetRegistry =3D bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY as isize, + GspSetSystemInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INF= O as isize, + GspInitPostObjGpu =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJ= GPU as isize, + GspRmControl =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL as isiz= e, + GetStaticInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO as is= ize, + + // Event codes + GspInitDone =3D bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE as isize, + GspRunCpuSequencer =3D bindings::NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENC= ER as isize, + PostEvent =3D bindings::NV_VGPU_MSG_EVENT_POST_EVENT as isize, + RcTriggered =3D bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED as isize, + MmuFaultQueued =3D bindings::NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED as isi= ze, + OsErrorLog =3D bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG as isize, + GspPostNoCat =3D bindings::NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD as = isize, + GspLockdownNotice =3D bindings::NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE = as isize, + UcodeLibOsPrint =3D bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT as i= size, +} + +impl fmt::Display for MsgFunction { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + // Common function codes + MsgFunction::Nop =3D> write!(f, "NOP"), + MsgFunction::SetGuestSystemInfo =3D> write!(f, "SET_GUEST_SYST= EM_INFO"), + MsgFunction::AllocRoot =3D> write!(f, "ALLOC_ROOT"), + MsgFunction::AllocDevice =3D> write!(f, "ALLOC_DEVICE"), + MsgFunction::AllocMemory =3D> write!(f, "ALLOC_MEMORY"), + MsgFunction::AllocCtxDma =3D> write!(f, "ALLOC_CTX_DMA"), + MsgFunction::AllocChannelDma =3D> write!(f, "ALLOC_CHANNEL_DMA= "), + MsgFunction::MapMemory =3D> write!(f, "MAP_MEMORY"), + MsgFunction::BindCtxDma =3D> write!(f, "BIND_CTX_DMA"), + MsgFunction::AllocObject =3D> write!(f, "ALLOC_OBJECT"), + MsgFunction::Free =3D> write!(f, "FREE"), + MsgFunction::Log =3D> write!(f, "LOG"), + MsgFunction::GetGspStaticInfo =3D> write!(f, "GET_GSP_STATIC_I= NFO"), + MsgFunction::SetRegistry =3D> write!(f, "SET_REGISTRY"), + MsgFunction::GspSetSystemInfo =3D> write!(f, "GSP_SET_SYSTEM_I= NFO"), + MsgFunction::GspInitPostObjGpu =3D> write!(f, "GSP_INIT_POST_O= BJGPU"), + MsgFunction::GspRmControl =3D> write!(f, "GSP_RM_CONTROL"), + MsgFunction::GetStaticInfo =3D> write!(f, "GET_STATIC_INFO"), + + // Event codes + MsgFunction::GspInitDone =3D> write!(f, "INIT_DONE"), + MsgFunction::GspRunCpuSequencer =3D> write!(f, "RUN_CPU_SEQUEN= CER"), + MsgFunction::PostEvent =3D> write!(f, "POST_EVENT"), + MsgFunction::RcTriggered =3D> write!(f, "RC_TRIGGERED"), + MsgFunction::MmuFaultQueued =3D> write!(f, "MMU_FAULT_QUEUED"), + MsgFunction::OsErrorLog =3D> write!(f, "OS_ERROR_LOG"), + MsgFunction::GspPostNoCat =3D> write!(f, "NOCAT"), + MsgFunction::GspLockdownNotice =3D> write!(f, "LOCKDOWN_NOTICE= "), + MsgFunction::UcodeLibOsPrint =3D> write!(f, "LIBOS_PRINT"), + } + } +} + +impl TryFrom for MsgFunction { + type Error =3D kernel::error::Error; + + fn try_from(value: u32) -> Result { + match value { + bindings::NV_VGPU_MSG_FUNCTION_NOP =3D> Ok(MsgFunction::Nop), + bindings::NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO =3D> { + Ok(MsgFunction::SetGuestSystemInfo) + } + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_ROOT =3D> Ok(MsgFunction:= :AllocRoot), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE =3D> Ok(MsgFunctio= n::AllocDevice), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY =3D> Ok(MsgFunctio= n::AllocMemory), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA =3D> Ok(MsgFuncti= on::AllocCtxDma), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA =3D> Ok(MsgFu= nction::AllocChannelDma), + bindings::NV_VGPU_MSG_FUNCTION_MAP_MEMORY =3D> Ok(MsgFunction:= :MapMemory), + bindings::NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA =3D> Ok(MsgFunctio= n::BindCtxDma), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT =3D> Ok(MsgFunctio= n::AllocObject), + bindings::NV_VGPU_MSG_FUNCTION_FREE =3D> Ok(MsgFunction::Free), + bindings::NV_VGPU_MSG_FUNCTION_LOG =3D> Ok(MsgFunction::Log), + bindings::NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO =3D> Ok(Msg= Function::GetGspStaticInfo), + bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY =3D> Ok(MsgFunctio= n::SetRegistry), + bindings::NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO =3D> Ok(Msg= Function::GspSetSystemInfo), + bindings::NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU =3D> { + Ok(MsgFunction::GspInitPostObjGpu) + } + bindings::NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL =3D> Ok(MsgFunct= ion::GspRmControl), + bindings::NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO =3D> Ok(MsgFunc= tion::GetStaticInfo), + bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE =3D> Ok(MsgFunction:= :GspInitDone), + bindings::NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER =3D> { + Ok(MsgFunction::GspRunCpuSequencer) + } + bindings::NV_VGPU_MSG_EVENT_POST_EVENT =3D> Ok(MsgFunction::Po= stEvent), + bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED =3D> Ok(MsgFunction::= RcTriggered), + bindings::NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED =3D> Ok(MsgFuncti= on::MmuFaultQueued), + bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG =3D> Ok(MsgFunction::= OsErrorLog), + bindings::NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD =3D> Ok(MsgF= unction::GspPostNoCat), + bindings::NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE =3D> Ok(MsgFun= ction::GspLockdownNotice), + bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT =3D> Ok(MsgFunct= ion::UcodeLibOsPrint), + _ =3D> Err(EINVAL), + } + } +} + #[repr(transparent)] pub(crate) struct LibosMemoryRegionInitArgument(bindings::LibosMemoryRegio= nInitArgument); =20 @@ -191,3 +308,148 @@ fn id8(name: &str) -> u64 { }) } } + +#[repr(transparent)] +pub(crate) struct MsgqTxHeader(bindings::msgqTxHeader); + +impl MsgqTxHeader { + pub(crate) fn new(msgq_size: u32, rx_hdr_offset: u32, msg_count: u32) = -> Self { + Self(bindings::msgqTxHeader { + version: 0, + size: msgq_size, + msgSize: GSP_PAGE_SIZE as u32, + msgCount: msg_count, + writePtr: 0, + flags: 1, + rxHdrOff: rx_hdr_offset, + entryOff: GSP_PAGE_SIZE as u32, + }) + } + + pub(crate) fn write_ptr(&self) -> u32 { + let ptr =3D (&self.0.writePtr) as *const u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_read! macro would and is therefore s= afe + // for the same reasons. + unsafe { ptr.read_volatile() } + } + + pub(crate) fn set_write_ptr(&mut self, val: u32) { + let ptr =3D (&mut self.0.writePtr) as *mut u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_write! macro would and is therefore = safe + // for the same reasons. + unsafe { ptr.write_volatile(val) } + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for MsgqTxHeader {} + +/// RX header for setting up a message queue with the GSP. +#[repr(transparent)] +pub(crate) struct MsgqRxHeader(bindings::msgqRxHeader); + +impl MsgqRxHeader { + pub(crate) fn new() -> Self { + Self(Default::default()) + } + + pub(crate) fn read_ptr(&self) -> u32 { + let ptr =3D (&self.0.readPtr) as *const u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_read! macro would and is therefore s= afe + // for the same reasons. + unsafe { ptr.read_volatile() } + } + + pub(crate) fn set_read_ptr(&mut self, val: u32) { + let ptr =3D (&mut self.0.readPtr) as *mut u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_write! macro would and is therefore = safe + // for the same reasons. + unsafe { ptr.write_volatile(val) } + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for MsgqRxHeader {} + +#[repr(transparent)] +pub(crate) struct GspRpcHeader(bindings::rpc_message_header_v); + +impl GspRpcHeader { + pub(crate) fn new(cmd_size: u32, function: u32) -> Self { + Self(bindings::rpc_message_header_v { + // TODO: magic number + header_version: 0x03000000, + signature: bindings::NV_VGPU_MSG_SIGNATURE_VALID, + function, + // We don't ever expect to send a command large enough to over= flow. + length: (size_of::() as u32).checked_add(cmd_size).unwra= p(), + rpc_result: 0xffffffff, + rpc_result_private: 0xffffffff, + ..Default::default() + }) + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspRpcHeader {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspRpcHeader {} + +#[repr(transparent)] +pub(crate) struct GspMsgElement(bindings::GSP_MSG_QUEUE_ELEMENT); + +impl GspMsgElement { + pub(crate) fn new(sequence: u32, cmd_size: usize, function: u32) -> Se= lf { + Self(bindings::GSP_MSG_QUEUE_ELEMENT { + seqNum: sequence, + // TODO: overflow check and fallible div? + elemCount: (size_of::() + cmd_size).div_ceil(GSP_PAGE_SI= ZE) as u32, + // TODO: fallible conversion. + rpc: GspRpcHeader::new(cmd_size as u32, function).0, + ..Default::default() + }) + } + + pub(crate) fn set_checksum(&mut self, checksum: u32) { + self.0.checkSum =3D checksum; + } + + // Return the total length of the message, noting that rpc.length incl= udes + // the length of the GspRpcHeader but not the message header. + pub(crate) fn length(&self) -> u32 { + size_of::() as u32 - size_of::() as u32 + self= .0.rpc.length + } + + pub(crate) fn sequence(&self) -> u32 { + self.0.rpc.sequence + } + + pub(crate) fn function_number(&self) -> u32 { + self.0.rpc.function + } + + pub(crate) fn function(&self) -> Result { + self.0.rpc.function.try_into() + } + + pub(crate) fn element_count(&self) -> u32 { + self.0.elemCount + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspMsgElement {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspMsgElement {} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 392b25dc6991..3d96d91e5b12 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -1,5 +1,36 @@ // SPDX-License-Identifier: GPL-2.0 =20 +#[repr(C)] +#[derive(Default)] +pub struct __IncompleteArrayField(::core::marker::PhantomData, [T; 0= ]); +impl __IncompleteArrayField { + #[inline] + pub const fn new() -> Self { + __IncompleteArrayField(::core::marker::PhantomData, []) + } + #[inline] + pub fn as_ptr(&self) -> *const T { + self as *const _ as *const T + } + #[inline] + pub fn as_mut_ptr(&mut self) -> *mut T { + self as *mut _ as *mut T + } + #[inline] + pub unsafe fn as_slice(&self, len: usize) -> &[T] { + ::core::slice::from_raw_parts(self.as_ptr(), len) + } + #[inline] + pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] { + ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len) + } +} +impl ::core::fmt::Debug for __IncompleteArrayField { + fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Re= sult { + fmt.write_str("__IncompleteArrayField") + } +} +pub const NV_VGPU_MSG_SIGNATURE_VALID: u32 =3D 1129337430; pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 =3D 0; pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 =3D 23068672; pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 =3D 8388608; @@ -19,6 +50,312 @@ pub type u16_ =3D __u16; pub type u32_ =3D __u32; pub type u64_ =3D __u64; +pub const NV_VGPU_MSG_FUNCTION_NOP: _bindgen_ty_2 =3D 0; +pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO: _bindgen_ty_2 =3D 1; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_ROOT: _bindgen_ty_2 =3D 2; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE: _bindgen_ty_2 =3D 3; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY: _bindgen_ty_2 =3D 4; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA: _bindgen_ty_2 =3D 5; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA: _bindgen_ty_2 =3D 6; +pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY: _bindgen_ty_2 =3D 7; +pub const NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA: _bindgen_ty_2 =3D 8; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT: _bindgen_ty_2 =3D 9; +pub const NV_VGPU_MSG_FUNCTION_FREE: _bindgen_ty_2 =3D 10; +pub const NV_VGPU_MSG_FUNCTION_LOG: _bindgen_ty_2 =3D 11; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM: _bindgen_ty_2 =3D 12; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY: _bindgen_ty_2 =3D 13; +pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA: _bindgen_ty_2 =3D 14; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA: _bindgen_ty_2 =3D 15; +pub const NV_VGPU_MSG_FUNCTION_GET_EDID: _bindgen_ty_2 =3D 16; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL: _bindgen_ty_2 =3D 17; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT: _bindgen_ty_2 =3D 18; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE: _bindgen_ty_2 =3D 19; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY: _bindgen_ty_2 =3D 20; +pub const NV_VGPU_MSG_FUNCTION_DUP_OBJECT: _bindgen_ty_2 =3D 21; +pub const NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS: _bindgen_ty_2 =3D 22; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_EVENT: _bindgen_ty_2 =3D 23; +pub const NV_VGPU_MSG_FUNCTION_SEND_EVENT: _bindgen_ty_2 =3D 24; +pub const NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL: _bindgen_ty_2 =3D 25; +pub const NV_VGPU_MSG_FUNCTION_DMA_CONTROL: _bindgen_ty_2 =3D 26; +pub const NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM: _bindgen_ty_2 =3D 27; +pub const NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE: _bindgen_ty_2 =3D 28; +pub const NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA: _bindgen_ty_2 =3D 2= 9; +pub const NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT: _bindgen_ty_2 =3D 30; +pub const NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT: _bindgen_ty_2 =3D 31; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE: _bindgen_ty_2 =3D 32; +pub const NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL: _bindgen_ty_2 =3D 33; +pub const NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API: _bindgen_ty_2 =3D 34; +pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ: _bindgen_ty_2 =3D 35; +pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE: _bindgen_ty_2 =3D 36; +pub const NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA: _bindgen_ty= _2 =3D 37; +pub const NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT: _bindgen_ty_2 =3D 38; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO: _bindgen_ty_2 =3D 39; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE: _bindgen_ty_2 =3D = 40; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO: _bindgen_ty_2= =3D 41; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO: _bindgen_ty_2 =3D 42; +pub const NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY: _bindgen_ty_2 =3D 43; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY: _bindgen_ty_2 =3D 44; +pub const NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES: _bindgen_ty_2 =3D 4= 5; +pub const NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE: _bindgen_ty_2 =3D 46; +pub const NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER: _bindgen_ty_2 =3D 4= 7; +pub const NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE: _bindgen_ty_2 =3D 48; +pub const NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA: _bindgen_ty_2 =3D 49; +pub const NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS: _bindgen_ty_2 =3D 50; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO: _bindgen_ty_2 =3D 51; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM: _bindgen_ty_2 =3D 52; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2: _bindgen_ty_2 =3D 53; +pub const NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY: _bindgen_ty_2 =3D 54; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO: _bindgen_ty_2 =3D 5= 5; +pub const NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES: _bindgen_ty_2 =3D= 56; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_57: _bindgen_ty_2 =3D 57; +pub const NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT: _bindgen_ty_2 =3D= 58; +pub const NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE: _bindgen_ty_= 2 =3D 59; +pub const NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION: _bindgen_ty_2 =3D 6= 0; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES: _bindgen_ty_2 =3D 61; +pub const NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY: _bindgen_ty_2 =3D 62; +pub const NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32: _bindgen_ty_2 =3D 63; +pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT: _bindgen_ty_2 = =3D 64; +pub const NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO: _bindgen_ty_2 =3D 65; +pub const NV_VGPU_MSG_FUNCTION_RMFS_INIT: _bindgen_ty_2 =3D 66; +pub const NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE: _bindgen_ty_2 =3D 67; +pub const NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP: _bindgen_ty_2 =3D 68; +pub const NV_VGPU_MSG_FUNCTION_RMFS_TEST: _bindgen_ty_2 =3D 69; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE: _bindgen_ty_2 =3D 70; +pub const NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD: _bindgen_ty_2 =3D 71; +pub const NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO: _bindgen_ty_2 =3D 72; +pub const NV_VGPU_MSG_FUNCTION_SET_REGISTRY: _bindgen_ty_2 =3D 73; +pub const NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU: _bindgen_ty_2 =3D 74; +pub const NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION: _bindgen_ty_= 2 =3D 75; +pub const NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: _bindgen_ty_2 =3D 76; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2: _bindgen_ty_2 =3D 77; +pub const NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT: _bindgen_ty_2 =3D = 78; +pub const NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY: _bindgen_ty_2 =3D 79; +pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO: _bindgen_ty_2= =3D 80; +pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER: _bindgen_ty_2 = =3D 81; +pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER: _bindgen_ty_2= =3D 82; +pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER: _= bindgen_ty_2 =3D 83; +pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER:= _bindgen_ty_2 =3D 84; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE: _bindgen_ty_2 =3D 8= 5; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO: _bindgen= _ty_2 =3D 86; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO: _bindgen= _ty_2 =3D 87; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL: _bindgen_ty_2 =3D 88; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL: _bindgen_ty_2 = =3D 89; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT: _bindgen_ty_2= =3D 90; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO: _bindgen_ty_2 = =3D 91; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST: _bindgen_ty_2 =3D 92; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL: _bindgen_ty= _2 =3D 93; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE: _bindgen_ty_2 =3D= 94; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR: _bindgen_ty_2 =3D= 95; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR: _bindgen_ty_2 =3D= 96; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE: _bindgen_ty_2 =3D 97; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE: _bindgen_ty_2 =3D 98; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT: _bindgen_ty_2 =3D 99; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS: _bindgen_ty_2 = =3D 100; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL: _bindgen_ty_= 2 =3D 101; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL: _bindgen= _ty_2 =3D 102; +pub const NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: _bindgen_ty_2 =3D 103; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2: _bindgen_ty_2 =3D 104; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT: _bindgen_ty_2 =3D = 105; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY: _bindgen_ty_2 =3D = 106; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS: _bindgen_ty= _2 =3D 107; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES: _bindge= n_ty_2 =3D 108; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES: _bindgen= _ty_2 =3D 109; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK: _bindgen_ty_2 = =3D 110; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX: _bindgen_ty_2 =3D 111; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND: _bindgen_ty_= 2 =3D 112; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE: _bindgen= _ty_2 =3D 113; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND: _bindgen_ty_2 =3D= 114; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX: _bindgen_ty_2 =3D = 115; +pub const NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES: _bi= ndgen_ty_2 =3D 116; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT: _bindgen_ty_2 = =3D 117; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES: _bindgen_ty_= 2 =3D 118; +pub const NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS: _bindgen_ty_2 = =3D 119; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE: _bindgen_ty_2= =3D 120; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK: _bindgen_ty_2 =3D 121; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY: _bindgen_ty= _2 =3D 122; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK: _bindgen_ty_2= =3D 123; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS: _bindgen_ty_2 =3D 1= 24; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS: _bindgen_ty_2 =3D 125; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX: _bindgen_ty_2 =3D= 126; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_0: _bindgen_ty_2 =3D 127; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC: _bindgen_ty_2 = =3D 128; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY: _bindgen_ty_2 =3D= 129; +pub const NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS: _bindgen_ty_2 =3D 1= 30; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES: _bindgen_ty_2 =3D 1= 31; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT: _bindgen_ty_2 =3D= 132; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT: _bindgen_ty_2 =3D = 133; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS: _bindgen_ty_2 =3D 13= 4; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG: _bindgen_ty_2 = =3D 135; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE: _bindg= en_ty_2 =3D 136; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE: _bind= gen_ty_2 =3D 137; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG: _bindgen_ty= _2 =3D 138; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE: _bindg= en_ty_2 =3D 139; +pub const NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM: _bindgen_ty_2 =3D 14= 0; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT: _bindgen_ty= _2 =3D 141; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2: _bindgen_ty_2 =3D 142; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES: _bindgen_= ty_2 =3D 143; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = =3D 144; +pub const NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES: _bindgen_ty_2= =3D 145; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX: _bindgen_ty_2 =3D 146; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO: _bindgen_ty_2 =3D 147; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO: _bindgen_ty_2 = =3D 148; +pub const NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL: _bindgen_ty_2 =3D 149; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE: _bindgen_ty_2 =3D= 150; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS: _bindgen_ty= _2 =3D 151; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL: _bindgen_t= y_2 =3D 152; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM: _bindgen_ty_2 =3D 153; +pub const NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ: _bindgen_ty_2 = =3D 154; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB: _bind= gen_ty_2 =3D 155; +pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO: _bindgen_t= y_2 =3D 156; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP: _bindge= n_ty_2 =3D 157; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE: _bindgen_ty= _2 =3D 158; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE: _bindgen_ty= _2 =3D 159; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE: _bindgen_ty_2 = =3D 160; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY: _bindgen_ty_2 = =3D 161; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP: _bindgen_ty_2 =3D 1= 62; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP: _bindgen_ty_2 =3D= 163; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM: _bindgen_ty= _2 =3D 164; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES: _bindgen_ty= _2 =3D 165; +pub const NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION: _b= indgen_ty_2 =3D 166; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL: _bindgen= _ty_2 =3D 167; +pub const NV_VGPU_MSG_FUNCTION_DCE_RM_INIT: _bindgen_ty_2 =3D 168; +pub const NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER: _bindgen_ty_= 2 =3D 169; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET: _bindgen_ty_2= =3D 170; +pub const NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND: _bindgen_ty_2 =3D= 171; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2: _bindgen_ty= _2 =3D 172; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM: _bi= ndgen_ty_2 =3D 173; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE: _bindgen_ty_2 =3D = 174; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS:= _bindgen_ty_2 =3D 175; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE: _bindgen_ty_= 2 =3D 176; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO: _bindgen_ty_= 2 =3D 177; +pub const NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS: _bindgen_ty_2 =3D 178; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE: _bindgen_ty_2 = =3D 179; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS: _bindgen_ty_2 =3D 18= 0; +pub const NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA: _bindgen_ty_2 =3D 18= 1; +pub const NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA: _bindgen_ty_2 =3D= 182; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED: _b= indgen_ty_2 =3D 183; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE: _bindgen_ty_2 = =3D 184; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE: _bindgen_ty_2 = =3D 185; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN: _bindgen= _ty_2 =3D 186; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_IND= EX: _bindgen_ty_2 =3D 187; +pub const NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPER= ATION: _bindgen_ty_2 =3D + 188; +pub const NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT= _INTR_MASK: + _bindgen_ty_2 =3D 189; +pub const NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER: _bin= dgen_ty_2 =3D 190; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS: _bindgen_ty_2 = =3D 191; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING: _bindgen_ty_2 =3D= 192; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING: _bindgen_ty_2 = =3D 193; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK: _bindgen= _ty_2 =3D 194; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS: _bindgen_ty_2 =3D = 195; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS: _bindgen_ty_2 = =3D 196; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS: _bindgen_ty_2 =3D 197; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS: _bindgen_ty_2 =3D 198; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER: _bindgen_ty_2 =3D = 199; +pub const NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB: _bindgen_ty_2 =3D 200; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS: _bindgen_ty_2 = =3D 201; +pub const NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK: _bindgen_ty_2 =3D 2= 02; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG: _bindgen_ty_2 = =3D 203; +pub const NV_VGPU_MSG_FUNCTION_RM_API_CONTROL: _bindgen_ty_2 =3D 204; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE: _= bindgen_ty_2 =3D 205; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA: _bind= gen_ty_2 =3D 206; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA: _bindgen_ty_2 =3D 207; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_208: _bindgen_ty_2 =3D 208; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2: _bindgen_ty_2 =3D 209; +pub const NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS: _bindgen_ty_2 =3D 210; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA: _bindgen_= ty_2 =3D 211; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO: _bindgen_ty_2= =3D 212; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE: _bindg= en_ty_2 =3D 213; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR: _bindgen_ty_2 = =3D 214; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS: _bindge= n_ty_2 =3D 215; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS: _bindg= en_ty_2 =3D 216; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG: _bindgen_t= y_2 =3D 217; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG: _bindgen_t= y_2 =3D 218; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES: _bindgen_ty_2 =3D 219; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES: _bindgen_ty_2 =3D 220; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF: _bindgen_ty_2 =3D 22= 1; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF: _bindgen_ty_2 =3D 22= 2; +pub const NV_VGPU_MSG_FUNCTION_RESERVED: _bindgen_ty_2 =3D 223; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL: _bindg= en_ty_2 =3D 224; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_HS_CREDITS_MAPPING: _bindgen_t= y_2 =3D 225; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_EXPORT: _bindgen_ty_2 = =3D 226; +pub const NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS: _bindgen_ty_2 =3D 227; +pub type _bindgen_ty_2 =3D ffi::c_uint; +pub const NV_VGPU_MSG_EVENT_FIRST_EVENT: _bindgen_ty_3 =3D 4096; +pub const NV_VGPU_MSG_EVENT_GSP_INIT_DONE: _bindgen_ty_3 =3D 4097; +pub const NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: _bindgen_ty_3 =3D 4098; +pub const NV_VGPU_MSG_EVENT_POST_EVENT: _bindgen_ty_3 =3D 4099; +pub const NV_VGPU_MSG_EVENT_RC_TRIGGERED: _bindgen_ty_3 =3D 4100; +pub const NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED: _bindgen_ty_3 =3D 4101; +pub const NV_VGPU_MSG_EVENT_OS_ERROR_LOG: _bindgen_ty_3 =3D 4102; +pub const NV_VGPU_MSG_EVENT_RG_LINE_INTR: _bindgen_ty_3 =3D 4103; +pub const NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES: _bindgen_ty_3 = =3D 4104; +pub const NV_VGPU_MSG_EVENT_SIM_READ: _bindgen_ty_3 =3D 4105; +pub const NV_VGPU_MSG_EVENT_SIM_WRITE: _bindgen_ty_3 =3D 4106; +pub const NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK: _bindgen_ty_3 =3D= 4107; +pub const NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT: _bindgen_ty_3 =3D 4108; +pub const NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: _bindgen_ty_3 =3D 4= 109; +pub const NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK: _bindgen_= ty_3 =3D 4110; +pub const NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE: _bindgen_ty_3 =3D= 4111; +pub const NV_VGPU_MSG_EVENT_VGPU_CONFIG: _bindgen_ty_3 =3D 4112; +pub const NV_VGPU_MSG_EVENT_DISPLAY_MODESET: _bindgen_ty_3 =3D 4113; +pub const NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE: _bindgen_ty_3 =3D 4114; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _bindgen_ty_3= =3D 4115; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512: _bindgen_ty_3= =3D 4116; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024: _bindgen_ty_= 3 =3D 4117; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048: _bindgen_ty_= 3 =3D 4118; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096: _bindgen_ty_= 3 =3D 4119; +pub const NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE: _bindgen_ty_3 =3D 412= 0; +pub const NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED: _bindgen_ty_3 =3D 4121; +pub const NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK: _bindgen_ty= _3 =3D 4122; +pub const NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: _bindgen_ty_3 =3D 4123; +pub const NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _bindgen_ty_3 =3D 4124; +pub const NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: _bindgen_ty_3 =3D 4125; +pub const NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE: _bindgen_ty_3 =3D 4126; +pub const NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY: _bindgen_ty_3 =3D= 4127; +pub const NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: _bindgen_ty_3 =3D 4128; +pub const NV_VGPU_MSG_EVENT_FECS_ERROR: _bindgen_ty_3 =3D 4129; +pub const NV_VGPU_MSG_EVENT_RECOVERY_ACTION: _bindgen_ty_3 =3D 4130; +pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 =3D 4131; +pub type _bindgen_ty_3 =3D ffi::c_uint; +#[repr(C)] +#[derive(Copy, Clone)] +pub union rpc_message_rpc_union_field_v03_00 { + pub spare: u32_, + pub cpuRmGfid: u32_, +} +impl Default for rpc_message_rpc_union_field_v03_00 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +pub type rpc_message_rpc_union_field_v =3D rpc_message_rpc_union_field_v03= _00; +#[repr(C)] +pub struct rpc_message_header_v03_00 { + pub header_version: u32_, + pub signature: u32_, + pub length: u32_, + pub function: u32_, + pub rpc_result: u32_, + pub rpc_result_private: u32_, + pub sequence: u32_, + pub u: rpc_message_rpc_union_field_v, + pub rpc_message_data: __IncompleteArrayField, +} +impl Default for rpc_message_header_v03_00 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +pub type rpc_message_header_v =3D rpc_message_header_v03_00; #[repr(C)] #[derive(Copy, Clone)] pub struct GspFwWprMeta { @@ -145,3 +482,40 @@ pub struct LibosMemoryRegionInitArgument { pub loc: u8_, pub __bindgen_padding_0: [u8; 6usize], } +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct msgqTxHeader { + pub version: u32_, + pub size: u32_, + pub msgSize: u32_, + pub msgCount: u32_, + pub writePtr: u32_, + pub flags: u32_, + pub rxHdrOff: u32_, + pub entryOff: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct msgqRxHeader { + pub readPtr: u32_, +} +#[repr(C)] +#[repr(align(8))] +pub struct GSP_MSG_QUEUE_ELEMENT { + pub authTagBuffer: [u8_; 16usize], + pub aadBuffer: [u8_; 16usize], + pub checkSum: u32_, + pub seqNum: u32_, + pub elemCount: u32_, + pub __bindgen_padding_0: [u8; 4usize], + pub rpc: rpc_message_header_v, +} +impl Default for GSP_MSG_QUEUE_ELEMENT { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); 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charset="utf-8" This commit introduces core infrastructure for handling GSP command and message queues in the nova-core driver. The command queue system enables bidirectional communication between the host driver and GSP firmware through a remote message passing interface. The interface is based on passing serialised data structures over a ring buffer with separate transmit and receive queues. Commands are sent by writing to the CPU transmit queue and waiting for completion via the receive queue. To ensure safety mutable or immutable (depending on whether it is a send or receive operation) references are taken on the command queue when allocating the message to write/read to. This ensures message memory remains valid and the command queue can't be mutated whilst an operation is in progress. Currently this is only used by the probe() routine and therefore can only used by a single thread of execution. Locking to enable safe access from multiple threads will be introduced in a future series when that becomes necessary. Signed-off-by: Alistair Popple --- There are still a couple of TODOs left to address here, in particular switching to using `init!` (see "gpu: nova-core: Add bindings and accessors for GspSystemInfo" for why that hasn't been done yet) and a couple of other minor refactors of the send/receive functions which have been pointed out in v2 (eg. methods to extract a command region, etc.) Changes for v3: - Reduce the receive payloads to the correct size - Use opaque bindings - Clean up of the command queue PTE creation - Add an enum for the GSP functions - Rename GspCommandToGsp and GspMessageFromGsp - Rename GspCmdq - Add function to notify GSP of updated queue pointers - Inline driver area access functions - Fixup receive area calculations Changes for v2: - Rebased on Alex's latest series --- drivers/gpu/nova-core/gsp.rs | 10 + drivers/gpu/nova-core/gsp/cmdq.rs | 402 ++++++++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 4 + drivers/gpu/nova-core/sbuffer.rs | 2 - scripts/Makefile.build | 2 +- 5 files changed, 417 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nova-core/gsp/cmdq.rs diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 537a226f98d0..3132f1009897 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -5,6 +5,7 @@ =20 pub(crate) use fw::{GspFwWprMeta, LibosParams}; =20 +use kernel::alloc::flags::GFP_KERNEL; use kernel::device; use kernel::dma::CoherentAllocation; use kernel::dma::DmaAddress; @@ -15,8 +16,12 @@ use kernel::transmute::AsBytes; =20 use crate::fb::FbLayout; +use crate::gsp::cmdq::Cmdq; + use fw::LibosMemoryRegionInitArgument; =20 +pub(crate) mod cmdq; + pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; pub(crate) const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new::<{ 1 <<= 20 }>(); @@ -31,6 +36,7 @@ pub(crate) struct Gsp { pub loginit: CoherentAllocation, pub logintr: CoherentAllocation, pub logrm: CoherentAllocation, + pub cmdq: Cmdq, } =20 #[repr(C)] @@ -85,11 +91,15 @@ pub(crate) fn new(pdev: &pci::Device) ->= Result() =3D=3D GSP_PAGE_SIZE); + +// There is no struct defined for this in the open-gpu-kernel-source heade= rs. +// Instead it is defined by code in GspMsgQueuesInit(). +#[repr(C)] +struct Msgq { + tx: MsgqTxHeader, + rx: MsgqRxHeader, + msgq: MsgqData, +} + +#[repr(C)] +struct GspMem { + ptes: PteArray<{ GSP_PAGE_SIZE / size_of::() }>, + cpuq: Msgq, + gspq: Msgq, +} + +// SAFETY: These structs don't meet the no-padding requirements of AsBytes= but +// that is not a problem because they are not used outside the kernel. +unsafe impl AsBytes for GspMem {} + +// SAFETY: These structs don't meet the no-padding requirements of FromByt= es but +// that is not a problem because they are not used outside the kernel. +unsafe impl FromBytes for GspMem {} + +/// `GspMem` struct that is shared with the GSP. +struct DmaGspMem(CoherentAllocation); + +impl DmaGspMem { + fn new(dev: &device::Device) -> Result { + const MSGQ_SIZE: u32 =3D size_of::() as u32; + const RX_HDR_OFF: u32 =3D offset_of!(Msgq, rx) as u32; + + let gsp_mem =3D + CoherentAllocation::::alloc_coherent(dev, 1, GFP_KERNE= L | __GFP_ZERO)?; + dma_write!(gsp_mem[0].ptes =3D PteArray::new(gsp_mem.dma_handle())= )?; + dma_write!(gsp_mem[0].cpuq.tx =3D MsgqTxHeader::new(MSGQ_SIZE, RX_= HDR_OFF, MSGQ_NUM_PAGES))?; + dma_write!(gsp_mem[0].cpuq.rx =3D MsgqRxHeader::new())?; + + Ok(Self(gsp_mem)) + } + + fn driver_write_area(&mut self) -> (&mut [[u8; GSP_PAGE_SIZE]], &mut [= [u8; GSP_PAGE_SIZE]]) { + let tx =3D self.cpu_write_ptr() as usize; + let rx =3D self.gsp_read_ptr() as usize; + + // SAFETY: + // - The [`CoherentAllocation`] contains exactly one object. + // - We will only access the driver-owned part of the shared memor= y. + // - Per the safety statement of the function, no concurrent acces= s wil be performed. + let gsp_mem =3D &mut unsafe { self.0.as_slice_mut(0, 1) }.unwrap()= [0]; + let (before_tx, after_tx) =3D gsp_mem.cpuq.msgq.data.split_at_mut(= tx); + + if rx <=3D tx { + // The area from `tx` up to the end of the ring, and from the = beginning of the ring up + // to `rx`, minus one unit, belongs to the driver. + if rx =3D=3D 0 { + let last =3D after_tx.len() - 1; + (&mut after_tx[..last], &mut before_tx[0..0]) + } else { + (after_tx, &mut before_tx[..rx]) + } + } else { + // The area from `tx` to `rx`, minus one unit, belongs to the = driver. + (after_tx.split_at_mut(rx - tx).0, &mut before_tx[0..0]) + } + } + + fn driver_read_area(&self) -> (&[[u8; GSP_PAGE_SIZE]], &[[u8; GSP_PAGE= _SIZE]]) { + let tx =3D self.gsp_write_ptr() as usize; + let rx =3D self.cpu_read_ptr() as usize; + + // SAFETY: + // - The [`CoherentAllocation`] contains exactly one object. + // - We will only access the driver-owned part of the shared memor= y. + // - Per the safety statement of the function, no concurrent acces= s wil be performed. + let gsp_mem =3D &unsafe { self.0.as_slice(0, 1) }.unwrap()[0]; + let (before_rx, after_rx) =3D gsp_mem.gspq.msgq.data.split_at(rx); + + if tx =3D=3D rx { + (&after_rx[0..0], &after_rx[0..0]) + } else if tx > rx { + (&after_rx[..tx], &before_rx[0..0]) + } else { + (after_rx, &before_rx[..tx]) + } + } + + fn gsp_write_ptr(&self) -> u32 { + let gsp_mem =3D self.0.start_ptr(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + (unsafe { (*gsp_mem).gspq.tx.write_ptr() } % MSGQ_NUM_PAGES) + // dma_read!(gsp_mem[0].gspq.tx.writePtr).unwrap() % MSGQ_NUM_PAGES + } + + fn gsp_read_ptr(&self) -> u32 { + let gsp_mem =3D self.0.start_ptr(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + (unsafe { (*gsp_mem).gspq.rx.read_ptr() } % MSGQ_NUM_PAGES) + } + + fn cpu_read_ptr(&self) -> u32 { + let gsp_mem =3D self.0.start_ptr(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + (unsafe { (*gsp_mem).cpuq.rx.read_ptr() } % MSGQ_NUM_PAGES) + } + + /// Inform the GSP that it can send `elem_count` new pages into the me= ssage queue. + fn advance_cpu_read_ptr(&mut self, elem_count: u32) { + // let gsp_mem =3D &self.0; + let rptr =3D self.cpu_read_ptr().wrapping_add(elem_count) % MSGQ_N= UM_PAGES; + + // Ensure read pointer is properly ordered + fence(Ordering::SeqCst); + + let gsp_mem =3D self.0.start_ptr_mut(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + unsafe { (*gsp_mem).cpuq.rx.set_read_ptr(rptr) }; + } + + fn cpu_write_ptr(&self) -> u32 { + let gsp_mem =3D self.0.start_ptr(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + (unsafe { (*gsp_mem).cpuq.tx.write_ptr() } % MSGQ_NUM_PAGES) + } + + /// Inform the GSP that it can process `elem_count` new pages from the= command queue. + fn advance_cpu_write_ptr(&mut self, elem_count: u32) { + let wptr =3D self.cpu_write_ptr().wrapping_add(elem_count) & MSGQ_= NUM_PAGES; + let gsp_mem =3D self.0.start_ptr_mut(); + + // SAFETY: + // - The ['CoherentAllocation'] contains at least one object. + // - By the invariants of CoherentAllocation the pointer is valid. + unsafe { (*gsp_mem).cpuq.tx.set_write_ptr(wptr) }; + + // Ensure all command data is visible before triggering the GSP re= ad + fence(Ordering::SeqCst); + } +} + +pub(crate) struct Cmdq { + dev: ARef, + seq: u32, + gsp_mem: DmaGspMem, + pub _nr_ptes: u32, +} + +impl Cmdq { + pub(crate) fn new(dev: &device::Device) -> Result= { + let gsp_mem =3D DmaGspMem::new(dev)?; + let nr_ptes =3D size_of::() >> GSP_PAGE_SHIFT; + build_assert!(nr_ptes * size_of::() <=3D GSP_PAGE_SIZE); + + Ok(Cmdq { + dev: dev.into(), + seq: 0, + gsp_mem, + _nr_ptes: nr_ptes as u32, + }) + } + + fn calculate_checksum>(it: T) -> u32 { + let sum64 =3D it + .enumerate() + .map(|(idx, byte)| (((idx % 8) * 8) as u32, byte)) + .fold(0, |acc, (rol, byte)| acc ^ u64::from(byte).rotate_left(= rol)); + + ((sum64 >> 32) as u32) ^ (sum64 as u32) + } + + // Notify GSP that we have updated the command queue pointers. + fn notify_gsp(bar: &Bar0) { + NV_PGSP_QUEUE_HEAD::default().set_address(0).write(bar); + } + + #[expect(unused)] + pub(crate) fn send_gsp_command( + &mut self, + bar: &Bar0, + payload_size: usize, + init: impl FnOnce(&mut M, SBuffer>) -> Result, + ) -> Result { + // TODO: a method that extracts the regions for a given command? + // ... and another that reduces the region to a given number of by= tes! + let driver_area =3D self.gsp_mem.driver_write_area(); + let free_tx_pages =3D driver_area.0.len() + driver_area.1.len(); + + // Total size of the message, including the headers, command, and = optional payload. + let msg_size =3D size_of::() + size_of::() + pay= load_size; + if free_tx_pages < msg_size.div_ceil(GSP_PAGE_SIZE) { + return Err(EAGAIN); + } + + let (msg_header, cmd, payload_1, payload_2) =3D { + #[allow(clippy::incompatible_msrv)] + let (msg_header_slice, slice_1) =3D driver_area + .0 + .as_flattened_mut() + .split_at_mut(size_of::()); + let msg_header =3D GspMsgElement::from_bytes_mut(msg_header_sl= ice).ok_or(EINVAL)?; + let (cmd_slice, payload_1) =3D slice_1.split_at_mut(size_of::<= M>()); + let cmd =3D M::from_bytes_mut(cmd_slice).ok_or(EINVAL)?; + #[allow(clippy::incompatible_msrv)] + let payload_2 =3D driver_area.1.as_flattened_mut(); + // TODO: Replace this workaround to cut the payload size. + let (payload_1, payload_2) =3D match payload_size.checked_sub(= payload_1.len()) { + // The payload is longer than `payload_1`, set `payload_2`= size to the difference. + Some(payload_2_len) =3D> (payload_1, &mut payload_2[..payl= oad_2_len]), + // `payload_1` is longer than the payload, we need to redu= ce its size. + None =3D> (&mut payload_1[..payload_size], payload_2), + }; + + (msg_header, cmd, payload_1, payload_2) + }; + + let sbuffer =3D SBuffer::new_writer([&mut payload_1[..], &mut payl= oad_2[..]]); + init(cmd, sbuffer)?; + + *msg_header =3D + GspMsgElement::new(self.seq, size_of::() + payload_size, M:= :FUNCTION as u32); + msg_header.set_checksum(Cmdq::calculate_checksum(SBuffer::new_read= er([ + msg_header.as_bytes(), + cmd.as_bytes(), + payload_1, + payload_2, + ]))); + + dev_info!( + &self.dev, + "GSP RPC: send: seq# {}, function=3D0x{:x} ({}), length=3D0x{:= x}\n", + self.seq, + msg_header.function_number(), + msg_header.function()?, + msg_header.length(), + ); + + let elem_count =3D msg_header.element_count(); + self.seq +=3D 1; + self.gsp_mem.advance_cpu_write_ptr(elem_count); + Cmdq::notify_gsp(bar); + + Ok(()) + } + + #[expect(unused)] + pub(crate) fn receive_msg_from_gsp( + &mut self, + timeout: Delta, + init: impl FnOnce(&M, SBuffer>) ->= Result, + ) -> Result { + // TODO: use read_poll_timeout instead and error if we don't get t= he + // whole message. + let (driver_area, msg_header, slice_1) =3D wait_on(timeout, || { + let driver_area =3D self.gsp_mem.driver_read_area(); + if driver_area.0.is_empty() { + return None; + } + + #[allow(clippy::incompatible_msrv)] + let (msg_header_slice, slice_1) =3D driver_area + .0 + .as_flattened() + .split_at(size_of::()); + let msg_header =3D GspMsgElement::from_bytes(msg_header_slice)= .unwrap(); + if msg_header.length() < size_of::() as u32 { + return None; + } + + Some((driver_area, msg_header, slice_1)) + })?; + + let function: MsgFunction =3D msg_header.function().map_err(|_| { + dev_info!( + self.dev, + "GSP RPC: receive: seq# {}, bad function=3D0x{:x}, length= =3D0x{:x}\n", + msg_header.sequence(), + msg_header.function_number(), + msg_header.length(), + ); + EIO + })?; + + // Log RPC receive with message type decoding + dev_info!( + self.dev, + "GSP RPC: receive: seq# {}, function=3D0x{:x} ({}), length=3D0= x{:x}\n", + msg_header.sequence(), + msg_header.function_number(), + function, + msg_header.length(), + ); + + let (cmd_slice, payload_1) =3D slice_1.split_at(size_of::()); + #[allow(clippy::incompatible_msrv)] + let payload_2 =3D driver_area.1.as_flattened(); + + // Cut the payload slice(s) down to the actual length of the paylo= ad. + let (cmd_payload_1, cmd_payload_2) =3D + if payload_1.len() > msg_header.length() as usize - size_of::<= M>() { + ( + payload_1 + .split_at(msg_header.length() as usize - size_of::= ()) + .0, + &payload_2[0..0], + ) + } else { + ( + payload_1, + payload_2 + .split_at(msg_header.length() as usize - size_of::= () - payload_1.len()) + .0, + ) + }; + + if Cmdq::calculate_checksum(SBuffer::new_reader([ + msg_header.as_bytes(), + cmd_slice, + cmd_payload_1, + cmd_payload_2, + ])) !=3D 0 + { + dev_err!( + self.dev, + "GSP RPC: receive: Call {} - bad checksum", + msg_header.sequence() + ); + return Err(EIO); + } + + let result =3D if function =3D=3D M::FUNCTION { + let cmd =3D M::from_bytes(cmd_slice).ok_or(EINVAL)?; + let sbuffer =3D SBuffer::new_reader([cmd_payload_1, cmd_payloa= d_2]); + init(cmd, sbuffer) + } else { + Err(ERANGE) + }; + + self.gsp_mem + .advance_cpu_read_ptr(msg_header.length().div_ceil(GSP_PAGE_SI= ZE as u32)); + result + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 206dab2e1335..0585699ae951 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -71,6 +71,10 @@ pub(crate) fn chipset(self) -> Result { 30:30 ecc_mode_enabled as bool; }); =20 +register!(NV_PGSP_QUEUE_HEAD @ 0x00110c00 { + 31:0 address as u32; +}); + impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { /// Returns the usable framebuffer size, in bytes. pub(crate) fn usable_fb_size(self) -> u64 { diff --git a/drivers/gpu/nova-core/sbuffer.rs b/drivers/gpu/nova-core/sbuff= er.rs index e82f9d97ad21..bde80cc3fa63 100644 --- a/drivers/gpu/nova-core/sbuffer.rs +++ b/drivers/gpu/nova-core/sbuffer.rs @@ -37,7 +37,6 @@ impl<'a, I> SBuffer where I: Iterator, { - #[expect(unused)] pub(crate) fn new_reader(slices: impl IntoIterator) ->= Self where I: Iterator, @@ -45,7 +44,6 @@ pub(crate) fn new_reader(slices: impl IntoIterator) -> Self Self::new(slices) } =20 - #[expect(unused)] pub(crate) fn new_writer(slices: impl IntoIterator) ->= Self where I: Iterator, diff --git a/scripts/Makefile.build b/scripts/Makefile.build index d0ee33a487be..4ac6304332b6 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -317,7 +317,7 @@ $(obj)/%.lst: $(obj)/%.c FORCE # # Please see https://github.com/Rust-for-Linux/linux/issues/2 for details = on # the unstable features in use. -rust_allowed_features :=3D asm_const,asm_goto,arbitrary_self_types,lint_re= asons,offset_of_nested,raw_ref_op,used_with_arg +rust_allowed_features :=3D asm_const,asm_goto,arbitrary_self_types,lint_re= asons,offset_of_nested,raw_ref_op,used_with_arg,slice_flatten =20 # `--out-dir` is required to avoid temporaries being created by `rustc` in= the # current working directory, which may be not accessible in the out-of-tree --=20 2.50.1 From nobody Thu Oct 2 05:06:28 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011040.outbound.protection.outlook.com [40.93.194.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 494832FC895; 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charset="utf-8" Initialise the GSP resource manager arguments (rmargs) which provide initialisation parameters to the GSP firmware during boot. The rmargs structure contains arguments to configure the GSP message/command queue location. These are mapped for coherent DMA and added to the libos data structure for access when booting GSP. Signed-off-by: Alistair Popple --- Changes for v2: - Rebased on Alex's latest series --- drivers/gpu/nova-core/gsp.rs | 16 +++++ drivers/gpu/nova-core/gsp/cmdq.rs | 24 +++++++- drivers/gpu/nova-core/gsp/fw.rs | 60 +++++++++++++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 33 ++++++++++ 4 files changed, 130 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 3132f1009897..9e5dd9e5a316 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -3,6 +3,7 @@ mod boot; mod fw; =20 +use fw::GspArgumentsCached; pub(crate) use fw::{GspFwWprMeta, LibosParams}; =20 use kernel::alloc::flags::GFP_KERNEL; @@ -37,6 +38,7 @@ pub(crate) struct Gsp { pub logintr: CoherentAllocation, pub logrm: CoherentAllocation, pub cmdq: Cmdq, + rmargs: CoherentAllocation, } =20 #[repr(C)] @@ -93,12 +95,26 @@ pub(crate) fn new(pdev: &pci::Device) ->= Result::alloc_coh= erent( + dev, + 1, + GFP_KERNEL | __GFP_ZERO, + )?; + dma_write!(libos[3] =3D LibosMemoryRegionInitArgument::new("RMARGS= ", &rmargs))?; + + dma_write!( + rmargs[0] =3D fw::GspArgumentsCached::new( + fw::MessageQueueInitArguments::new(&cmdq), + fw::GspSrInitArguments::new() + ) + )?; =20 Ok(try_pin_init!(Self { libos, loginit, logintr, logrm, + rmargs, cmdq, })) } diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/= cmdq.rs index 7d43dc987ba2..2fd6b31db9e9 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -6,7 +6,7 @@ =20 use kernel::alloc::flags::GFP_KERNEL; use kernel::device; -use kernel::dma::CoherentAllocation; +use kernel::dma::{CoherentAllocation, DmaAddress}; use kernel::dma_write; use kernel::prelude::*; use kernel::sync::aref::ARef; @@ -202,10 +202,25 @@ pub(crate) struct Cmdq { dev: ARef, seq: u32, gsp_mem: DmaGspMem, - pub _nr_ptes: u32, } =20 impl Cmdq { + /// Offset of the data after the PTEs. + const POST_PTE_OFFSET: usize =3D core::mem::offset_of!(GspMem, cpuq); + + /// Offset of command queue ring buffer. + pub(crate) const CMDQ_OFFSET: usize =3D core::mem::offset_of!(GspMem, = cpuq) + + core::mem::offset_of!(Msgq, msgq) + - Self::POST_PTE_OFFSET; + + /// Offset of message queue ring buffer. + pub(crate) const STATQ_OFFSET: usize =3D core::mem::offset_of!(GspMem,= gspq) + + core::mem::offset_of!(Msgq, msgq) + - Self::POST_PTE_OFFSET; + + /// Number of page table entries for the GSP shared region. + pub(crate) const NUM_PTES: usize =3D size_of::() >> GSP_PAGE_S= HIFT; + pub(crate) fn new(dev: &device::Device) -> Result= { let gsp_mem =3D DmaGspMem::new(dev)?; let nr_ptes =3D size_of::() >> GSP_PAGE_SHIFT; @@ -215,7 +230,6 @@ pub(crate) fn new(dev: &device::Device) = -> Result { dev: dev.into(), seq: 0, gsp_mem, - _nr_ptes: nr_ptes as u32, }) } =20 @@ -399,4 +413,8 @@ pub(crate) fn receive_msg_from_gsp( .advance_cpu_read_ptr(msg_header.length().div_ceil(GSP_PAGE_SI= ZE as u32)); result } + + pub(crate) fn dma_handle(&self) -> DmaAddress { + self.gsp_mem.0.dma_handle() + } } diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index ee86abe7ea10..aec0db50adea 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -17,6 +17,7 @@ use crate::firmware::gsp::GspFirmware; use crate::gpu::Chipset; use crate::gsp; +use crate::gsp::cmdq::Cmdq; use crate::gsp::FbLayout; use crate::gsp::GSP_PAGE_SIZE; =20 @@ -453,3 +454,62 @@ unsafe impl AsBytes for GspMsgElement {} // SAFETY: This struct only contains integer types for which all bit patte= rns // are valid. unsafe impl FromBytes for GspMsgElement {} + +#[repr(transparent)] +pub(crate) struct GspArgumentsCached(bindings::GSP_ARGUMENTS_CACHED); + +impl GspArgumentsCached { + pub(crate) fn new( + queue_arguments: MessageQueueInitArguments, + sr_arguments: GspSrInitArguments, + ) -> Self { + Self(bindings::GSP_ARGUMENTS_CACHED { + messageQueueInitArguments: queue_arguments.0, + srInitArguments: sr_arguments.0, + bDmemStack: 1, + ..Default::default() + }) + } +} + +impl From for bindings::GSP_ARGUMENTS_CACHED { + fn from(value: GspArgumentsCached) -> Self { + value.0 + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspArgumentsCached {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspArgumentsCached {} + +#[repr(transparent)] +pub(crate) struct MessageQueueInitArguments(bindings::MESSAGE_QUEUE_INIT_A= RGUMENTS); + +impl MessageQueueInitArguments { + pub(crate) fn new(cmdq: &Cmdq) -> Self { + Self(bindings::MESSAGE_QUEUE_INIT_ARGUMENTS { + sharedMemPhysAddr: cmdq.dma_handle(), + pageTableEntryCount: Cmdq::NUM_PTES as u32, + cmdQueueOffset: Cmdq::CMDQ_OFFSET as u64, + statQueueOffset: Cmdq::STATQ_OFFSET as u64, + ..Default::default() + }) + } +} + +#[repr(transparent)] +pub(crate) struct GspSrInitArguments(bindings::GSP_SR_INIT_ARGUMENTS); + +impl GspSrInitArguments { + pub(crate) fn new() -> Self { + Self(bindings::GSP_SR_INIT_ARGUMENTS { + oldLevel: 0, + flags: 0, + bInPMTransition: 0, + ..Default::default() + }) + } +} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 3d96d91e5b12..b87c4e6cb857 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -319,6 +319,39 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) ->= ::core::fmt::Result { pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 =3D 4131; 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charset="utf-8" Adds bindings and an in-place initialiser for the GspSystemInfo struct. Signed-off-by: Alistair Popple --- It would be good to move to using the `init!` macros at some point, but I couldn't figure out how to make that work to initialise an enum rather than a struct as is required for the transparent representation. Changes for v3: - New for v3 --- drivers/gpu/nova-core/gsp/fw.rs | 1 + drivers/gpu/nova-core/gsp/fw/commands.rs | 40 ++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 132 ++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/gpu/nova-core/gsp/fw/commands.rs diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index aec0db50adea..2ef9d4acd6f9 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 =20 +pub(crate) mod commands; mod r570_144; =20 // Alias to avoid repeating the version number with every use. diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs new file mode 100644 index 000000000000..f28779af2620 --- /dev/null +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -0,0 +1,40 @@ +use super::bindings; + +use kernel::prelude::*; +use kernel::transmute::{AsBytes, FromBytes}; +use kernel::{device, pci}; + +#[repr(transparent)] +pub(crate) struct GspSystemInfo(bindings::GspSystemInfo); + +impl GspSystemInfo { + pub(crate) fn init(&mut self, dev: &pci::Device) -> Res= ult { + self.0.gpuPhysAddr =3D dev.resource_start(0)?; + self.0.gpuPhysFbAddr =3D dev.resource_start(1)?; + self.0.gpuPhysInstAddr =3D dev.resource_start(3)?; + self.0.nvDomainBusDeviceFunc =3D u64::from(dev.dev_id()); + + // Using TASK_SIZE in r535_gsp_rpc_set_system_info() seems wrong b= ecause + // TASK_SIZE is per-task. That's probably a design issue in GSP-RM= though. + self.0.maxUserVa =3D (1 << 47) - 4096; + self.0.pciConfigMirrorBase =3D 0x088000; + self.0.pciConfigMirrorSize =3D 0x001000; + + self.0.PCIDeviceID =3D (u32::from(dev.device_id()) << 16) | u32::f= rom(dev.vendor_id()); + self.0.PCISubDeviceID =3D + (u32::from(dev.subsystem_device_id()) << 16) | u32::from(dev.s= ubsystem_vendor_id()); + self.0.PCIRevisionID =3D u32::from(dev.revision_id()); + self.0.bIsPrimary =3D 0; + self.0.bPreserveVideoMemoryAllocations =3D 0; + + Ok(()) + } +} + +// SAFETY: These structs don't meet the no-padding requirements of AsBytes= but +// that is not a problem because they are not used outside the ker= nel. +unsafe impl AsBytes for GspSystemInfo {} + +// SAFETY: These structs don't meet the no-padding requirements of FromByt= es but +// that is not a problem because they are not used outside the ker= nel. +unsafe impl FromBytes for GspSystemInfo {} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index b87c4e6cb857..427fff82f7c1 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -320,6 +320,138 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -= > ::core::fmt::Result { pub type _bindgen_ty_3 =3D ffi::c_uint; #[repr(C)] #[derive(Debug, Default, Copy, Clone)] +pub struct DOD_METHOD_DATA { + pub status: u32_, + pub acpiIdListLen: u32_, + pub acpiIdList: [u32_; 16usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct JT_METHOD_DATA { + pub status: u32_, + pub jtCaps: u32_, + pub jtRevId: u16_, + pub bSBIOSCaps: u8_, + pub __bindgen_padding_0: u8, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct MUX_METHOD_DATA_ELEMENT { + pub acpiId: u32_, + pub mode: u32_, + pub status: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct MUX_METHOD_DATA { + pub tableLen: u32_, + pub acpiIdMuxModeTable: [MUX_METHOD_DATA_ELEMENT; 16usize], + pub acpiIdMuxPartTable: [MUX_METHOD_DATA_ELEMENT; 16usize], + pub acpiIdMuxStateTable: [MUX_METHOD_DATA_ELEMENT; 16usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct CAPS_METHOD_DATA { + pub status: u32_, + pub optimusCaps: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct ACPI_METHOD_DATA { + pub bValid: u8_, + pub __bindgen_padding_0: [u8; 3usize], + pub dodMethodData: DOD_METHOD_DATA, + pub jtMethodData: JT_METHOD_DATA, + pub muxMethodData: MUX_METHOD_DATA, + pub capsMethodData: CAPS_METHOD_DATA, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct BUSINFO { + pub deviceID: u16_, + pub vendorID: u16_, + pub subdeviceID: u16_, + pub subvendorID: u16_, + pub revisionID: u8_, + pub __bindgen_padding_0: u8, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GSP_VF_INFO { + pub totalVFs: u32_, + pub firstVFOffset: u32_, + pub FirstVFBar0Address: u64_, + pub FirstVFBar1Address: u64_, + pub FirstVFBar2Address: u64_, + pub b64bitBar0: u8_, + pub b64bitBar1: u8_, + pub b64bitBar2: u8_, + pub __bindgen_padding_0: [u8; 5usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GSP_PCIE_CONFIG_REG { + pub linkCap: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspSystemInfo { + pub gpuPhysAddr: u64_, + pub gpuPhysFbAddr: u64_, + pub gpuPhysInstAddr: u64_, + pub gpuPhysIoAddr: u64_, + pub nvDomainBusDeviceFunc: u64_, + pub simAccessBufPhysAddr: u64_, + pub notifyOpSharedSurfacePhysAddr: u64_, + pub pcieAtomicsOpMask: u64_, + pub consoleMemSize: u64_, + pub maxUserVa: u64_, + pub pciConfigMirrorBase: u32_, + pub pciConfigMirrorSize: u32_, + pub PCIDeviceID: u32_, + pub PCISubDeviceID: u32_, + pub PCIRevisionID: u32_, + pub pcieAtomicsCplDeviceCapMask: u32_, + pub oorArch: u8_, + pub __bindgen_padding_0: [u8; 7usize], + pub clPdbProperties: u64_, + pub Chipset: u32_, + pub bGpuBehindBridge: u8_, + pub bFlrSupported: u8_, + pub b64bBar0Supported: u8_, + pub bMnocAvailable: u8_, + pub chipsetL1ssEnable: u32_, + pub bUpstreamL0sUnsupported: u8_, + pub bUpstreamL1Unsupported: u8_, + pub bUpstreamL1PorSupported: u8_, + pub bUpstreamL1PorMobileOnly: u8_, + pub bSystemHasMux: u8_, + pub upstreamAddressValid: u8_, + pub FHBBusInfo: BUSINFO, + pub chipsetIDInfo: BUSINFO, + pub __bindgen_padding_1: [u8; 2usize], + pub acpiMethodData: ACPI_METHOD_DATA, + pub hypervisorType: u32_, + pub bIsPassthru: u8_, + pub __bindgen_padding_2: [u8; 7usize], + pub sysTimerOffsetNs: u64_, + pub gspVFInfo: GSP_VF_INFO, + pub bIsPrimary: u8_, + pub isGridBuild: u8_, + pub __bindgen_padding_3: [u8; 2usize], + pub pcieConfigReg: GSP_PCIE_CONFIG_REG, + pub gridBuildCsp: u32_, + pub bPreserveVideoMemoryAllocations: u8_, + pub bTdrEventSupported: u8_, + pub bFeatureStretchVblankCapable: u8_, + pub bEnableDynamicGranularityPageArrays: u8_, + pub bClockBoostSupported: u8_, + pub bRouteDispIntrsToCPU: u8_, + pub __bindgen_padding_4: [u8; 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charset="utf-8" Adds bindings and constructors for PACKED_REGISTRY_TABLE and PACKED_REGISTRY_ENTRY structures. Signed-off-by: Alistair Popple --- Changes for v3: - New for v3 --- drivers/gpu/nova-core/gsp/fw/commands.rs | 40 +++++++++++++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 17 ++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index f28779af2620..3037425902f7 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -38,3 +38,43 @@ unsafe impl AsBytes for GspSystemInfo {} // SAFETY: These structs don't meet the no-padding requirements of FromByt= es but // that is not a problem because they are not used outside the ker= nel. unsafe impl FromBytes for GspSystemInfo {} + +#[repr(transparent)] +pub(crate) struct PackedRegistryEntry(bindings::PACKED_REGISTRY_ENTRY); + +impl PackedRegistryEntry { + pub(crate) fn new(offset: u32, value: u32) -> Self { + Self({ + bindings::PACKED_REGISTRY_ENTRY { + nameOffset: offset, + type_: bindings::REGISTRY_TABLE_ENTRY_TYPE_DWORD as u8, + __bindgen_padding_0: Default::default(), + data: value, + length: 0, + } + }) + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for PackedRegistryEntry {} + +#[repr(transparent)] +pub(crate) struct PackedRegistryTable(bindings::PACKED_REGISTRY_TABLE); + +impl PackedRegistryTable { + pub(crate) fn new(num_entries: u32, size: u32) -> Self { + Self(bindings::PACKED_REGISTRY_TABLE { + numEntries: num_entries, + size, + entries: Default::default(), + }) + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for PackedRegistryTable {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for PackedRegistryTable {} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 427fff82f7c1..7ad1981e471c 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -42,6 +42,7 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 =3D 280; pub const GSP_FW_WPR_META_REVISION: u32 =3D 1; pub const GSP_FW_WPR_META_MAGIC: i64 =3D -2577556379034558285; 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charset="utf-8" Add the RM registry and system information commands that enable the host driver to configure GSP firmware parameters during initialization. The RM registry is serialized into a packed format and sent via the command queue. For now only two parameters which are required to boot GSP are hardcoded. In future a kernel module parameter will be added to enable other parameters to be added. Also add the system info command, which provides required hardware information to the GSP. These commands use the GSP command queue infrastructure to issue commands to the GSP which is read during GSP boot. Signed-off-by: Alistair Popple Reviewed-by: Lyude Paul --- Changes for v3: - Use MsgFunction enum - Rename GspCmdq to Cmdq - Rename GspCommandToGsp to CommandToGsp - Rename GspMessageFromGsp to MessageFromGsp - Split bindings into separate patch Changes for v2: - Rebased on Alex's latest tree --- drivers/gpu/nova-core/gsp.rs | 1 + drivers/gpu/nova-core/gsp/boot.rs | 6 +- drivers/gpu/nova-core/gsp/cmdq.rs | 1 - drivers/gpu/nova-core/gsp/commands.rs | 101 ++++++++++++++++++++++++++ drivers/gpu/nova-core/sbuffer.rs | 1 - 5 files changed, 107 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nova-core/gsp/commands.rs diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 9e5dd9e5a316..1d5544d9dfb4 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -22,6 +22,7 @@ use fw::LibosMemoryRegionInitArgument; =20 pub(crate) mod cmdq; +pub(crate) mod commands; =20 pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 1d2448331d7a..0b306313ec53 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -16,6 +16,7 @@ FIRMWARE_VERSION, }; use crate::gpu::Chipset; +use crate::gsp::commands::{build_registry, set_system_info}; use crate::gsp::GspFwWprMeta; use crate::regs; use crate::vbios::Vbios; @@ -105,7 +106,7 @@ fn run_fwsec_frts( /// /// Upon return, the GSP is up and running, and its runtime object giv= en as return value. pub(crate) fn boot( - self: Pin<&mut Self>, + mut self: Pin<&mut Self>, pdev: &pci::Device, bar: &Bar0, chipset: Chipset, @@ -139,6 +140,9 @@ pub(crate) fn boot( CoherentAllocation::::alloc_coherent(dev, 1, GFP= _KERNEL | __GFP_ZERO)?; dma_write!(wpr_meta[0] =3D GspFwWprMeta::new(&gsp_fw, &fb_layout))= ?; =20 + set_system_info(&mut self.cmdq, pdev, bar)?; + build_registry(&mut self.cmdq, bar)?; + Ok(()) } } diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/= cmdq.rs index 2fd6b31db9e9..5580eaf52f7b 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -247,7 +247,6 @@ fn notify_gsp(bar: &Bar0) { NV_PGSP_QUEUE_HEAD::default().set_address(0).write(bar); } =20 - #[expect(unused)] pub(crate) fn send_gsp_command( &mut self, bar: &Bar0, diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs new file mode 100644 index 000000000000..69df8d4be353 --- /dev/null +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::build_assert; +use kernel::device; +use kernel::pci; +use kernel::prelude::*; +use kernel::transmute::AsBytes; + +use super::fw::commands::*; +use super::fw::MsgFunction; +use crate::driver::Bar0; +use crate::gsp::cmdq::Cmdq; +use crate::gsp::cmdq::CommandToGsp; +use crate::gsp::GSP_PAGE_SIZE; +use crate::sbuffer::SBuffer; + +const GSP_REGISTRY_NUM_ENTRIES: usize =3D 2; +pub(crate) struct RegistryEntry { + key: &'static str, + value: u32, +} + +pub(crate) struct RegistryTable { + entries: [RegistryEntry; GSP_REGISTRY_NUM_ENTRIES], +} + +impl CommandToGsp for PackedRegistryTable { + const FUNCTION: MsgFunction =3D MsgFunction::SetRegistry; +} + +impl RegistryTable { + fn write_payload<'a, I: Iterator>( + &self, + mut sbuffer: SBuffer, + ) -> Result { + let string_data_start_offset =3D size_of::() + + GSP_REGISTRY_NUM_ENTRIES * size_of::(); + + // Array for string data. + let mut string_data =3D KVec::new(); + + for entry in self.entries.iter().take(GSP_REGISTRY_NUM_ENTRIES) { + sbuffer.write_all( + PackedRegistryEntry::new( + (string_data_start_offset + string_data.len()) as u32, + entry.value, + ) + .as_bytes(), + )?; + + let key_bytes =3D entry.key.as_bytes(); + string_data.extend_from_slice(key_bytes, GFP_KERNEL)?; + string_data.push(0, GFP_KERNEL)?; + } + + sbuffer.write_all(string_data.as_slice()) + } + + fn size(&self) -> usize { + let mut key_size =3D 0; + for i in 0..GSP_REGISTRY_NUM_ENTRIES { + key_size +=3D self.entries[i].key.len() + 1; // +1 for NULL te= rminator + } + GSP_REGISTRY_NUM_ENTRIES * size_of::() + key_= size + } +} + +pub(crate) fn build_registry(cmdq: &mut Cmdq, bar: &Bar0) -> Result { + let registry =3D RegistryTable { + entries: [ + RegistryEntry { + key: "RMSecBusResetEnable", + value: 1, + }, + RegistryEntry { + key: "RMForcePcieConfigSave", + value: 1, + }, + ], + }; + + cmdq.send_gsp_command::(bar, registry.size(), |ta= ble, sbuffer| { + *table =3D PackedRegistryTable::new(GSP_REGISTRY_NUM_ENTRIES as u3= 2, registry.size() as u32); + registry.write_payload(sbuffer) + }) +} + +impl CommandToGsp for GspSystemInfo { + const FUNCTION: MsgFunction =3D MsgFunction::GspSetSystemInfo; +} + +pub(crate) fn set_system_info( + cmdq: &mut Cmdq, + dev: &pci::Device, + bar: &Bar0, +) -> Result { + build_assert!(size_of::() < GSP_PAGE_SIZE); + cmdq.send_gsp_command::(bar, 0, |info, _| GspSystemInfo= ::init(info, dev))?; + + Ok(()) +} diff --git a/drivers/gpu/nova-core/sbuffer.rs b/drivers/gpu/nova-core/sbuff= er.rs index bde80cc3fa63..5acfd005a86b 100644 --- a/drivers/gpu/nova-core/sbuffer.rs +++ b/drivers/gpu/nova-core/sbuffer.rs @@ -159,7 +159,6 @@ fn get_slice_mut(&mut self, len: usize) -> Option<&'a m= ut [u8]> { =20 /// Ideally we would implement `Write`, but it is not available in `co= re`. /// So mimic `std::io::Write::write_all`. - #[expect(unused)] pub(crate) fn write_all(&mut self, mut src: &[u8]) -> Result { while !src.is_empty() { match self.get_slice_mut(src.len()) { --=20 2.50.1 From nobody Thu Oct 2 05:06:28 2025 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013000.outbound.protection.outlook.com [40.107.201.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D43830594A; 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charset="utf-8" From: Joel Fernandes Add definition for RISCV_CPUCTL register and use it in a new falcon API to check if the RISC-V core of a Falcon is active. It is required by the sequencer to know if the GSP's RISCV processor is active. Signed-off-by: Joel Fernandes Reviewed-by: Lyude Paul --- drivers/gpu/nova-core/falcon.rs | 9 +++++++++ drivers/gpu/nova-core/regs.rs | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 37e6298195e4..c7907f16bcf4 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -610,4 +610,13 @@ pub(crate) fn signature_reg_fuse_version( self.hal .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_i= d) } + + /// Check if the RISC-V core is active. + /// + /// Returns `true` if the RISC-V core is active, `false` otherwise. + #[expect(unused)] + pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result { + let cpuctl =3D regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); + Ok(cpuctl.active_stat()) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0585699ae951..5df6a2bf42ad 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -324,6 +324,11 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { =20 // PRISCV =20 +register!(NV_PRISCV_RISCV_CPUCTL @ PFalconBase[0x00001388] { + 7:7 active_stat as bool; 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charset="utf-8" From: Joel Fernandes This will be needed by both the GSP boot code as well as GSP resume code in the sequencer. Signed-off-by: Joel Fernandes Reviewed-by: Lyude Paul --- drivers/gpu/nova-core/falcon.rs | 9 +++++++++ drivers/gpu/nova-core/regs.rs | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index c7907f16bcf4..0cb7821341ed 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -619,4 +619,13 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Re= sult { let cpuctl =3D regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); Ok(cpuctl.active_stat()) } + + /// Write the application version to the OS register. + #[expect(dead_code)] + pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) ->= Result<()> { + regs::NV_PFALCON_FALCON_OS::default() + .set_value(app_version) + .write(bar, &E::ID); + Ok(()) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 5df6a2bf42ad..d9212fa50197 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -215,6 +215,12 @@ pub(crate) fn vga_workspace_addr(self) -> Option { 31:0 value as u32; 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Tue, 30 Sep 2025 13:18:05 +0000 Received: from DS0PR12MB7726.namprd12.prod.outlook.com ([fe80::953f:2f80:90c5:67fe]) by DS0PR12MB7726.namprd12.prod.outlook.com ([fe80::953f:2f80:90c5:67fe%4]) with mapi id 15.20.9160.015; Tue, 30 Sep 2025 13:18:04 +0000 From: Alistair Popple To: rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, dakr@kernel.org, acourbot@nvidia.com Cc: Alistair Popple , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , John Hubbard , Joel Fernandes , Timur Tabi , linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org, Lyude Paul Subject: [PATCH v3 13/13] nova-core: gsp: Boot GSP Date: Tue, 30 Sep 2025 23:16:46 +1000 Message-ID: <20250930131648.411720-14-apopple@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250930131648.411720-1-apopple@nvidia.com> References: <20250930131648.411720-1-apopple@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SY5P300CA0056.AUSP300.PROD.OUTLOOK.COM (2603:10c6:10:1fe::20) To DS0PR12MB7726.namprd12.prod.outlook.com (2603:10b6:8:130::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB7726:EE_|MN0PR12MB6078:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c012c62-706a-4327-7da0-08de0023c9b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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charset="utf-8" Boot the GSP to the RISC-V active state. Completing the boot requires running the CPU sequencer which will be added in a future commit. Signed-off-by: Alistair Popple Reviewed-by: Lyude Paul --- Changes for v3: - Fixed minor nit from John - Added booter load error thanks to Timur's suggestion Changes for v2: - Rebased on Alex's latest tree --- drivers/gpu/nova-core/falcon.rs | 2 - drivers/gpu/nova-core/firmware/riscv.rs | 3 +- drivers/gpu/nova-core/gsp.rs | 2 +- drivers/gpu/nova-core/gsp/boot.rs | 64 ++++++++++++++++++++++++- 4 files changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 0cb7821341ed..960801f74bf1 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -614,14 +614,12 @@ pub(crate) fn signature_reg_fuse_version( /// Check if the RISC-V core is active. /// /// Returns `true` if the RISC-V core is active, `false` otherwise. - #[expect(unused)] pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result { let cpuctl =3D regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); Ok(cpuctl.active_stat()) } =20 /// Write the application version to the OS register. - #[expect(dead_code)] pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) ->= Result<()> { regs::NV_PFALCON_FALCON_OS::default() .set_value(app_version) diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs index dec33d2b631a..d1a9e027bac3 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -50,7 +50,6 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result { } =20 /// A parsed firmware for a RISC-V core, ready to be loaded and run. -#[expect(unused)] pub(crate) struct RiscvFirmware { /// Offset at which the code starts in the firmware image. pub code_offset: u32, @@ -59,7 +58,7 @@ pub(crate) struct RiscvFirmware { /// Offset at which the manifest starts in the firmware image. pub manifest_offset: u32, /// Application version. - app_version: u32, + pub app_version: u32, /// Device-mapped firmware image. pub ucode: DmaObject, } diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 1d5544d9dfb4..d5a33fbf8fb6 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -34,7 +34,7 @@ /// GSP runtime data. #[pin_data] pub(crate) struct Gsp { - libos: CoherentAllocation, + pub libos: CoherentAllocation, pub loginit: CoherentAllocation, pub logintr: CoherentAllocation, pub logrm: CoherentAllocation, diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 0b306313ec53..77e9adf80f20 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -5,6 +5,7 @@ use kernel::dma_write; use kernel::pci; use kernel::prelude::*; +use kernel::time::Delta; =20 use crate::driver::Bar0; use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; @@ -19,6 +20,7 @@ use crate::gsp::commands::{build_registry, set_system_info}; use crate::gsp::GspFwWprMeta; use crate::regs; +use crate::util; use crate::vbios::Vbios; =20 impl super::Gsp { @@ -127,7 +129,7 @@ pub(crate) fn boot( =20 Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?; =20 - let _booter_loader =3D BooterFirmware::new( + let booter_loader =3D BooterFirmware::new( dev, BooterKind::Loader, chipset, @@ -143,6 +145,66 @@ pub(crate) fn boot( set_system_info(&mut self.cmdq, pdev, bar)?; build_registry(&mut self.cmdq, bar)?; =20 + gsp_falcon.reset(bar)?; + let libos_handle =3D self.libos.dma_handle(); + let (mbox0, mbox1) =3D gsp_falcon.boot( + bar, + Some(libos_handle as u32), + Some((libos_handle >> 32) as u32), + )?; + dev_dbg!( + pdev.as_ref(), + "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", + mbox0, + mbox1 + ); + + dev_dbg!( + pdev.as_ref(), + "Using SEC2 to load and run the booter_load firmware...\n" + ); + + sec2_falcon.reset(bar)?; + sec2_falcon.dma_load(bar, &booter_loader)?; + let wpr_handle =3D wpr_meta.dma_handle(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + bar, + Some(wpr_handle as u32), + Some((wpr_handle >> 32) as u32), + )?; + dev_dbg!( + pdev.as_ref(), + "SEC2 MBOX0: {:#x}, MBOX1{:#x}\n", + mbox0, + mbox1 + ); + + if mbox0 !=3D 0 { + dev_err!( + pdev.as_ref(), + "Booter-load failed with error {:#x}\n", + mbox0 + ); + return Err(ENODEV); + } + + gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version)?; + + // Poll for RISC-V to become active before running sequencer + util::wait_on(Delta::from_secs(5), || { + if gsp_falcon.is_riscv_active(bar).unwrap_or(false) { + Some(()) + } else { + None + } + })?; + + dev_dbg!( + pdev.as_ref(), + "RISC-V active? {}\n", + gsp_falcon.is_riscv_active(bar)?, + ); + Ok(()) } } --=20 2.50.1