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Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Juergen Gross Subject: [PATCH v2 08/12] x86/extable: Add support for immediate form MSR instructions Date: Tue, 30 Sep 2025 09:03:52 +0200 Message-ID: <20250930070356.30695-9-jgross@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250930070356.30695-1-jgross@suse.com> References: <20250930070356.30695-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[11]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 Content-Type: text/plain; charset="utf-8" From: "Xin Li (Intel)" Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li --- arch/x86/include/asm/msr.h | 18 ++++++++++++++++++ arch/x86/mm/extable.c | 39 +++++++++++++++++++++++++++++++++----- 2 files changed, 52 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 71f41af11591..cf5205300266 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -56,6 +56,24 @@ static inline void do_trace_read_msr(u32 msr, u64 val, i= nt failed) {} static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} #endif =20 +/* + * Called only from an MSR fault handler, the instruction pointer points to + * the MSR access instruction that caused the fault. + */ +static __always_inline bool is_msr_imm_insn(void *ip) +{ + /* + * A full decoder for immediate form MSR instructions appears excessive. + */ +#ifdef CONFIG_X86_64 + const u8 msr_imm_insn_prefix[] =3D { 0xc4, 0xe7 }; + + return !memcmp(ip, msr_imm_insn_prefix, sizeof(msr_imm_insn_prefix)); +#else + return false; +#endif +} + /* * __rdmsr() and __wrmsr() are the two primitives which are the bare minim= um MSR * accessors and should not have any tracing or other functionality piggyb= acking diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 2fdc1f1f5adb..c021e4dbc69d 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -166,23 +166,52 @@ static bool ex_handler_uaccess(const struct exception= _table_entry *fixup, static bool ex_handler_msr(const struct exception_table_entry *fixup, struct pt_regs *regs, bool wrmsr, bool safe, int reg) { + bool imm_insn =3D is_msr_imm_insn((void *)regs->ip); + u32 msr; + + if (imm_insn) + /* + * The 32-bit immediate specifying a MSR is encoded into + * byte 5 ~ 8 of an immediate form MSR instruction. + */ + msr =3D *(u32 *)(regs->ip + 5); + else + msr =3D (u32)regs->cx; + if (__ONCE_LITE_IF(!safe && wrmsr)) { - pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08= x%08x) at rIP: 0x%lx (%pS)\n", - (unsigned int)regs->cx, (unsigned int)regs->dx, - (unsigned int)regs->ax, regs->ip, (void *)regs->ip); + /* + * To maintain consistency with existing RDMSR and WRMSR(NS) instruction= s, + * the register operand for immediate form MSR instructions is ALWAYS + * encoded as RAX in for reading or writing the MSR value. + */ + u64 msr_val =3D regs->ax; + + if (!imm_insn) { + /* + * On processors that support the Intel 64 architecture, the + * high-order 32 bits of each of RAX and RDX are ignored. + */ + msr_val &=3D 0xffffffff; + msr_val |=3D (u64)regs->dx << 32; + } + + pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%01= 6llx) at rIP: 0x%lx (%pS)\n", + msr, msr_val, regs->ip, (void *)regs->ip); show_stack_regs(regs); } =20 if (__ONCE_LITE_IF(!safe && !wrmsr)) { pr_warn("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)= \n", - (unsigned int)regs->cx, regs->ip, (void *)regs->ip); + msr, regs->ip, (void *)regs->ip); show_stack_regs(regs); } =20 if (!wrmsr) { /* Pretend that the read succeeded and returned 0. */ regs->ax =3D 0; - regs->dx =3D 0; + + if (!imm_insn) + regs->dx =3D 0; } =20 if (safe) --=20 2.51.0