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Peter Anvin" Subject: [PATCH v2 02/12] x86/sev: Replace call of native_wrmsr() with native_wrmsrq() Date: Tue, 30 Sep 2025 09:03:46 +0200 Message-ID: <20250930070356.30695-3-jgross@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250930070356.30695-1-jgross@suse.com> References: <20250930070356.30695-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; MIME_TRACE(0.00)[0:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[9]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 Content-Type: text/plain; charset="utf-8" In sev_es_wr_ghcb_msr() the 64 bit MSR value is split into 2 32 bit values in order to call native_wrmsr(), which will combine the values into a 64 bit value again. Just use native_wrmsrq() instead. Signed-off-by: Juergen Gross Reviewed-by: Nikunj A Dadhania --- V2: - new patch --- arch/x86/include/asm/sev-internal.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/include/asm/sev-internal.h b/arch/x86/include/asm/sev= -internal.h index 3dfd306d1c9e..f5d6fb3b5916 100644 --- a/arch/x86/include/asm/sev-internal.h +++ b/arch/x86/include/asm/sev-internal.h @@ -89,12 +89,7 @@ static inline u64 sev_es_rd_ghcb_msr(void) =20 static __always_inline void sev_es_wr_ghcb_msr(u64 val) { - u32 low, high; - - low =3D (u32)(val); - high =3D (u32)(val >> 32); - - native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high); + native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); } =20 void snp_register_ghcb_early(unsigned long paddr); --=20 2.51.0