From nobody Thu Oct 2 02:15:15 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA99819AD89 for ; Tue, 30 Sep 2025 00:51:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759193515; cv=none; b=GekJ09BrlCC5raPeLzrz1A0vIT65H4RXp0pdPT8EH5sZAdp+Mv3Vq7HE8KKBLlLzfPOIToFi24jh7we7xzmyide/oey1E03rDt86GSbrKH4KAV6CpfgxANWG3yjrgUpBGVWlOS3Mm7KQpmiH6vN6piB9YVqwOfWIOgswmmCKWDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759193515; c=relaxed/simple; bh=J5lLd/vuL6jZtvy0ljv8wT1z6W/jyQFZVqfO7u/SBDE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=ooKjZu5WSrNfV3FHgDOJIF9U1sk9yPrSlZjT2LrDCKRT1F6y8bGJhVTEmVu4IejfSfebDtuAP2DaxSD7w3rNYlGC7uh1KKIrVchMZSTPB3LxorASzf7VSlusv4VtBnzBLbIwo36lTmTDMhXqXqDRdViy2W7JDQmjO+OncvSwtUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=ST6QfN0H; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="ST6QfN0H" Received: from epcas2p1.samsung.com (unknown [182.195.41.53]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20250930005149epoutp0162594d7705e8bc0884249b0d22870158~p6S05LgXH0369003690epoutp01U for ; Tue, 30 Sep 2025 00:51:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250930005149epoutp0162594d7705e8bc0884249b0d22870158~p6S05LgXH0369003690epoutp01U DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1759193509; bh=tG27NdAYAB5zCAFtjok5lejCXpe+CazBoZAPMuwAwqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ST6QfN0HHB1rbr6c7dapTDTwA5WUrnxwKSB/6XeJLobWhoWvvq1SWWD4y6HQcUWqu CV8wKrrfnYlwQmEH3jRWUXIovGPbe0Zh+RGliU/qgAenawy4ZEmVZNo8CbyfEWkIq6 j5Dd3NUWg764kkQjS2WyNtWXanVlHkQvkah5SZug= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPS id 20250930005149epcas2p13a46c2af48aad5db4771276e23d85010~p6S0eZsHo0911009110epcas2p1f; Tue, 30 Sep 2025 00:51:49 +0000 (GMT) Received: from epcas2p3.samsung.com (unknown [182.195.38.210]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4cbKJP0Ty8z6B9mH; Tue, 30 Sep 2025 00:51:49 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20250930005148epcas2p19ffbb0ceaacac4d92e7d43936884dc70~p6Szlovxq0653306533epcas2p1p; Tue, 30 Sep 2025 00:51:48 +0000 (GMT) Received: from asswp60 (unknown [10.229.9.60]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250930005148epsmtip2e41cbc86a3b8acb29e03f6fbc05b5772~p6SzP5Ouq1112411124epsmtip2L; Tue, 30 Sep 2025 00:51:48 +0000 (GMT) From: Shin Son To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Henrik Grimler Cc: Shin Son , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/3] arm64: dts: exynosautov920: Add multiple sensors Date: Tue, 30 Sep 2025 09:51:39 +0900 Message-ID: <20250930005139.1424963-4-shin.son@samsung.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250930005139.1424963-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250930005148epcas2p19ffbb0ceaacac4d92e7d43936884dc70 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250930005148epcas2p19ffbb0ceaacac4d92e7d43936884dc70 References: <20250930005139.1424963-1-shin.son@samsung.com> Create a new exynosautov920-tmu.dtsi describing new TMU hardware and include it from exynosautov920.dtsi. The exynosautov920-tmu node uses the misc clock as its source. This TMU binding defines multiple thermal zones with a critical trip point at 125 degrees: tmu_top : cpus0-0, cpus0-1, cpus0-2, cpus0-3, cpus1-0, cpus1-1, cpus1-2, cpus1-3, cpus1-4, cpus1-5, cpus1-6, cpus1-7 tmu_sub0: cpus0-4, cpus0-5, cpus0-6, cpus0-7, cpus2-0, cpus2-1, cpus2-2, cpus2-3 tmu_sub1: gpu0, gpu1, gpu2, gpu3, npu0, npu1 Signed-off-by: Shin Son --- .../boot/dts/exynos/exynosautov920-tmu.dtsi | 377 ++++++++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 31 ++ 2 files changed, 408 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi b/arch/arm6= 4/boot/dts/exynos/exynosautov920-tmu.dtsi new file mode 100644 index 000000000000..641d142e0eeb --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAuto920 TMU configurations device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * + * Samsung's ExynosAuto920 SoC TMU(Thermal Managemenut Unit) are listed as + * device tree nodes in this file. + */ + +/ { + thermal-zones { + cpus0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 9>; + + trips { + cpus0_0_critical: cpus0-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 10>; + + trips { + cpus0_1_critical: cpus0-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 11>; + + trips { + cpus0_2_critical: cpus0-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 12>; + + trips { + cpus0_3_critical: cpus0-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-4-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 7>; + + trips { + cpus0_4_critical: cpus0-4-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-5-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 8>; + + trips { + cpus0_5_critical: cpus0-5-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 9>; + + trips { + cpus0_6_critical: cpus0-6-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 10>; + + trips { + cpus0_7_critical: cpus0-7-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + cpus1_0_critical: cpus1-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + cpus1_1_critical: cpus1-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 3>; + + trips { + cpus1_2_critical: cpus1-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 4>; + + trips { + cpus1_3_critical: cpus1-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-4-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 5>; + + trips { + cpus1_4_critical: cpus1-4-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-5-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 6>; + + trips { + cpus1_5_critical: cpus1-5-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 7>; + + trips { + cpus1_6_critical: cpus1-6-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 8>; + + trips { + cpus1_7_critical: cpus1-7-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 3>; + + trips { + cpus2_0_critical: cpus2-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 4>; + + trips { + cpus2_1_critical: cpus2-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 5>; + + trips { + cpus2_2_critical: cpus2-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 6>; + + trips { + cpus2_3_critical: cpus2-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 1>; + + trips { + gpu0_critical: gpu0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 2>; + + trips { + gpu1_critical: gpu1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 3>; + + trips { + gpu2_critical: gpu2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 4>; + + trips { + gpu3_critical: gpu3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + npu0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 6>; + + trips { + npu0_critical: npu0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + npu1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 7>; + + trips { + npu1_critical: npu1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..fba403e48aed 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -330,6 +330,36 @@ watchdog_cl1: watchdog@10070000 { samsung,cluster-index =3D <1>; }; =20 + tmu_top: tmu@100a0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100A0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <12>; + }; + + tmu_sub0: tmu@100b0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100B0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <10>; + }; + + tmu_sub1: tmu@100c0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100C0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <7>; + }; + gic: interrupt-controller@10400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; @@ -1507,3 +1537,4 @@ timer { }; =20 #include "exynosautov920-pinctrl.dtsi" +#include "exynosautov920-tmu.dtsi" --=20 2.50.1