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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2025 00:26:40.3066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05149ba9-3f20-417b-7346-08ddffb80683 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6190 Content-Type: text/plain; charset="utf-8" Support NVIDIA PMU that utilizes the optional event filter2 register. Reviewed-by: Ilkka Koskinen Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 176 +++++++++++++++++++------- 1 file changed, 133 insertions(+), 43 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ac91dc46501d..e06a06d3407b 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -40,10 +40,21 @@ =20 struct nv_cspmu_ctx { const char *name; - u32 filter_mask; - u32 filter_default_val; + struct attribute **event_attr; struct attribute **format_attr; + + u32 filter_mask; + u32 filter_default_val; + u32 filter2_mask; + u32 filter2_default_val; + + u32 (*get_filter)(const struct perf_event *event); + u32 (*get_filter2)(const struct perf_event *event); + + void *data; + + int (*init_data)(struct arm_cspmu *cspmu); }; =20 static struct attribute *scf_pmu_event_attrs[] =3D { @@ -144,6 +155,7 @@ static struct attribute *cnvlink_pmu_format_attrs[] =3D= { static struct attribute *generic_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, ARM_CSPMU_FORMAT_FILTER_ATTR, + ARM_CSPMU_FORMAT_FILTER2_ATTR, NULL, }; =20 @@ -184,13 +196,36 @@ static u32 nv_cspmu_event_filter(const struct perf_ev= ent *event) return filter_val; } =20 +static u32 nv_cspmu_event_filter2(const struct perf_event *event) +{ + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + + const u32 filter_val =3D event->attr.config2 & ctx->filter2_mask; + + if (filter_val =3D=3D 0) + return ctx->filter2_default_val; + + return filter_val; +} + static void nv_cspmu_set_ev_filter(struct arm_cspmu *cspmu, const struct perf_event *event) { - u32 filter =3D nv_cspmu_event_filter(event); - u32 offset =3D PMEVFILTR + (4 * event->hw.idx); + u32 filter, offset; + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + offset =3D 4 * event->hw.idx; =20 - writel(filter, cspmu->base0 + offset); + if (ctx->get_filter) { + filter =3D ctx->get_filter(event); + writel(filter, cspmu->base0 + PMEVFILTR + offset); + } + + if (ctx->get_filter2) { + filter =3D ctx->get_filter2(event); + writel(filter, cspmu->base0 + PMEVFILT2R + offset); + } } =20 static void nv_cspmu_set_cc_filter(struct arm_cspmu *cspmu, @@ -210,74 +245,120 @@ enum nv_cspmu_name_fmt { struct nv_cspmu_match { u32 prodid; u32 prodid_mask; - u64 filter_mask; - u32 filter_default_val; const char *name_pattern; enum nv_cspmu_name_fmt name_fmt; - struct attribute **event_attr; - struct attribute **format_attr; + struct nv_cspmu_ctx template_ctx; + struct arm_cspmu_impl_ops ops; }; =20 static const struct nv_cspmu_match nv_cspmu_match[] =3D { { .prodid =3D 0x10300000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_PCIE_FILTER_ID_MASK, - .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, .name_pattern =3D "nvidia_pcie_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D pcie_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D pcie_pmu_format_attrs, + .filter_mask =3D NV_PCIE_FILTER_ID_MASK, + .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10400000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10500000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10600000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_CNVL_FILTER_ID_MASK, - .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, .name_pattern =3D "nvidia_cnvlink_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D cnvlink_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D cnvlink_pmu_format_attrs, + .filter_mask =3D NV_CNVL_FILTER_ID_MASK, + .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x2CF00000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, - .filter_default_val =3D 0x0, .name_pattern =3D "nvidia_scf_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D scf_pmu_event_attrs, - .format_attr =3D scf_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D scf_pmu_event_attrs, + .format_attr =3D scf_pmu_format_attrs, + .filter_mask =3D 0x0, + .filter_default_val =3D 0x0, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0, .prodid_mask =3D 0, - .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, - .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, .name_pattern =3D "nvidia_uncore_pmu_%u", .name_fmt =3D NAME_FMT_GENERIC, - .event_attr =3D generic_pmu_event_attrs, - .format_attr =3D generic_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D generic_pmu_event_attrs, + .format_attr =3D generic_pmu_format_attrs, + .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D nv_cspmu_event_filter2, + .data =3D NULL, + .init_data =3D NULL + }, }, }; =20 @@ -310,6 +391,14 @@ static char *nv_cspmu_format_name(const struct arm_csp= mu *cspmu, return name; } =20 +#define SET_OP(name, impl, match, default_op) \ + do { \ + if (match->ops.name) \ + impl->name =3D match->ops.name; \ + else if (default_op !=3D NULL) \ + impl->name =3D default_op; \ + } while (false) + static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) { struct nv_cspmu_ctx *ctx; @@ -330,20 +419,21 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) break; } =20 - ctx->name =3D nv_cspmu_format_name(cspmu, match); - ctx->filter_mask =3D match->filter_mask; - ctx->filter_default_val =3D match->filter_default_val; - ctx->event_attr =3D match->event_attr; - ctx->format_attr =3D match->format_attr; + /* Initialize the context with the matched template. */ + memcpy(ctx, &match->template_ctx, sizeof(struct nv_cspmu_ctx)); + ctx->name =3D nv_cspmu_format_name(cspmu, match); =20 cspmu->impl.ctx =3D ctx; =20 /* NVIDIA specific callbacks. */ - impl_ops->set_cc_filter =3D nv_cspmu_set_cc_filter; - impl_ops->set_ev_filter =3D nv_cspmu_set_ev_filter; - impl_ops->get_event_attrs =3D nv_cspmu_get_event_attrs; - impl_ops->get_format_attrs =3D nv_cspmu_get_format_attrs; - impl_ops->get_name =3D nv_cspmu_get_name; + SET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter); + SET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter); + SET_OP(get_event_attrs, impl_ops, match, nv_cspmu_get_event_attrs); + SET_OP(get_format_attrs, impl_ops, match, nv_cspmu_get_format_attrs); + SET_OP(get_name, impl_ops, match, nv_cspmu_get_name); + + if (ctx->init_data) + return ctx->init_data(cspmu); =20 return 0; } --=20 2.50.1