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To streamline the identification of the correct struct for a gpu, move it to the catalogue and move the gpu_init routine to struct adreno_gpu_funcs. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 8 +- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 50 +++---- drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 14 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 52 +++---- drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 8 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 54 ++++---- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 18 +-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 61 ++++----- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 50 +++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 209 ++++++++++++++-----------= ---- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +- 12 files changed, 275 insertions(+), 262 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a2xx_catalog.c index 5ddd015f930d9a7dd04e2d2035daa0b2f5ff3f27..af3e4cceadd11d4e0ec4ba75f75= e405af276cb7e 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c @@ -8,6 +8,8 @@ =20 #include "adreno_gpu.h" =20 +extern const struct adreno_gpu_funcs a2xx_gpu_funcs; + static const struct adreno_info a2xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x02000000), @@ -19,7 +21,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, }, { /* a200 on i.mx51 has only 128kib gmem */ .chip_ids =3D ADRENO_CHIP_IDS(0x02000001), .family =3D ADRENO_2XX_GEN1, @@ -30,7 +32,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x02020000), .family =3D ADRENO_2XX_GEN2, @@ -41,7 +43,7 @@ static const struct adreno_info a2xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a2xx_gpu_init, + .funcs =3D &a2xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a2xx); diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index ec38db45d8a366e75acddbacd4810d7b7a80926f..7082052f715e69f1643860a5cce= 1c84aa4df5935 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -486,39 +486,18 @@ static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct = msm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a2xx_hw_init, - .pm_suspend =3D msm_gpu_pm_suspend, - .pm_resume =3D msm_gpu_pm_resume, - .recover =3D a2xx_recover, - .submit =3D a2xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a2xx_irq, - .destroy =3D a2xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_state_get =3D a2xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D a2xx_create_vm, - .get_rptr =3D a2xx_get_rptr, - }, -}; - static const struct msm_gpu_perfcntr perfcntrs[] =3D { /* TODO */ }; =20 -struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) { struct a2xx_gpu *a2xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; int ret; =20 if (!pdev) { @@ -539,7 +518,7 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) gpu->perfcntrs =3D perfcntrs; gpu->num_perfcntrs =3D ARRAY_SIZE(perfcntrs); =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -558,3 +537,26 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a2xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a2xx_hw_init, + .pm_suspend =3D msm_gpu_pm_suspend, + .pm_resume =3D msm_gpu_pm_resume, + .recover =3D a2xx_recover, + .submit =3D a2xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a2xx_irq, + .destroy =3D a2xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_state_get =3D a2xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D a2xx_create_vm, + .get_rptr =3D a2xx_get_rptr, + }, + .init =3D a2xx_gpu_init, +}; diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a3xx_catalog.c index 1498e6532f62c707754502c713b3bcc60a3c1478..02a9729756de8fb59541f57c715= b5661be7d3dac 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c @@ -8,6 +8,8 @@ =20 #include "adreno_gpu.h" =20 +extern const struct adreno_gpu_funcs a3xx_gpu_funcs; + static const struct adreno_info a3xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x03000512), @@ -18,7 +20,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000520), .family =3D ADRENO_3XX, @@ -29,7 +31,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000600), .family =3D ADRENO_3XX, @@ -40,7 +42,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x03000620), .family =3D ADRENO_3XX, @@ -51,7 +53,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS( 0x03020000, @@ -66,7 +68,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS( 0x03030000, @@ -81,7 +83,7 @@ static const struct adreno_info a3xx_gpus[] =3D { }, .gmem =3D SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a3xx_gpu_init, + .funcs =3D &a3xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a3xx); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index a956cd79195e0e13d6b2a1920b15e9aa12f1d060..f22d33e99e815ab3da0296366a9= 1f5c6e9f918ec 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -508,29 +508,6 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct m= sm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a3xx_hw_init, - .pm_suspend =3D msm_gpu_pm_suspend, - .pm_resume =3D msm_gpu_pm_resume, - .recover =3D a3xx_recover, - .submit =3D a3xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a3xx_irq, - .destroy =3D a3xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_busy =3D a3xx_gpu_busy, - .gpu_state_get =3D a3xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a3xx_get_rptr, - }, -}; - static const struct msm_gpu_perfcntr perfcntrs[] =3D { { REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO, SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" }, @@ -538,13 +515,14 @@ static const struct msm_gpu_perfcntr perfcntrs[] =3D { SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" }, }; =20 -struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) { struct a3xx_gpu *a3xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; struct icc_path *ocmem_icc_path; struct icc_path *icc_path; int ret; @@ -569,7 +547,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) =20 adreno_gpu->registers =3D a3xx_registers; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -613,3 +591,27 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a3xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a3xx_hw_init, + .pm_suspend =3D msm_gpu_pm_suspend, + .pm_resume =3D msm_gpu_pm_resume, + .recover =3D a3xx_recover, + .submit =3D a3xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a3xx_irq, + .destroy =3D a3xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_busy =3D a3xx_gpu_busy, + .gpu_state_get =3D a3xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a3xx_get_rptr, + }, + .init =3D a3xx_gpu_init, +}; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a4xx_catalog.c index 09f9f228b75e086d09f41b858a3d43dd7da6284d..160d86870568edfcd2aa335b1b7= c1d71c4673eae 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c @@ -8,6 +8,8 @@ =20 #include "adreno_gpu.h" =20 +extern const struct adreno_gpu_funcs a4xx_gpu_funcs; + static const struct adreno_info a4xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x04000500), @@ -19,7 +21,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D SZ_256K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x04020000), .family =3D ADRENO_4XX, @@ -30,7 +32,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D (SZ_1M + SZ_512K), .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x04030002), .family =3D ADRENO_4XX, @@ -41,7 +43,7 @@ static const struct adreno_info a4xx_gpus[] =3D { }, .gmem =3D (SZ_1M + SZ_512K), .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a4xx_gpu_init, + .funcs =3D &a4xx_gpu_funcs, } }; DECLARE_ADRENO_GPULIST(a4xx); diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index 83f6329accbacee076a583bdda9816e1cbcdfb59..db06c06067aeb2cf3e2b5da7b36= cac2bc31a7bee 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -627,37 +627,14 @@ static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct = msm_ringbuffer *ring) return ring->memptrs->rptr; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a4xx_hw_init, - .pm_suspend =3D a4xx_pm_suspend, - .pm_resume =3D a4xx_pm_resume, - .recover =3D a4xx_recover, - .submit =3D a4xx_submit, - .active_ring =3D adreno_active_ring, - .irq =3D a4xx_irq, - .destroy =3D a4xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D adreno_show, -#endif - .gpu_busy =3D a4xx_gpu_busy, - .gpu_state_get =3D a4xx_gpu_state_get, - .gpu_state_put =3D adreno_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a4xx_get_rptr, - }, - .get_timestamp =3D a4xx_get_timestamp, -}; - -struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) { struct a4xx_gpu *a4xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; + struct adreno_platform_config *config =3D pdev->dev.platform_data; struct icc_path *ocmem_icc_path; struct icc_path *icc_path; int ret; @@ -680,7 +657,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) gpu->perfcntrs =3D NULL; gpu->num_perfcntrs =3D 0; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1); if (ret) goto fail; =20 @@ -726,3 +703,28 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) =20 return ERR_PTR(ret); } + +const struct adreno_gpu_funcs a4xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a4xx_hw_init, + .pm_suspend =3D a4xx_pm_suspend, + .pm_resume =3D a4xx_pm_resume, + .recover =3D a4xx_recover, + .submit =3D a4xx_submit, + .active_ring =3D adreno_active_ring, + .irq =3D a4xx_irq, + .destroy =3D a4xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D adreno_show, +#endif + .gpu_busy =3D a4xx_gpu_busy, + .gpu_state_get =3D a4xx_gpu_state_get, + .gpu_state_put =3D adreno_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a4xx_get_rptr, + }, + .init =3D a4xx_gpu_init, + .get_timestamp =3D a4xx_get_timestamp, +}; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a5xx_catalog.c index b48a636d82370ec78e2869e9d5fa96c5c9f90a95..4ea5702824f273d64666c9c6dc6= 3c975b940d538 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -8,6 +8,8 @@ =20 #include "adreno_gpu.h" =20 +extern const struct adreno_gpu_funcs a5xx_gpu_funcs; + static const struct adreno_info a5xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x05000500), @@ -21,7 +23,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000600), .family =3D ADRENO_5XX, @@ -38,7 +40,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a506_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000800), @@ -55,7 +57,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a508_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05000900), @@ -72,7 +74,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, /* Adreno 509 uses the same ZAP as 512 */ .zapfw =3D "a512_zap.mdt", }, { @@ -89,7 +91,7 @@ static const struct adreno_info a5xx_gpus[] =3D { * the GDSC which appears to make it grumpy */ .inactive_period =3D 250, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05010200), .family =3D ADRENO_5XX, @@ -105,7 +107,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a512_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS( @@ -127,7 +129,7 @@ static const struct adreno_info a5xx_gpus[] =3D { .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_TWO_PASS_USE_WFI | ADRENO_QUIRK_FAULT_DETECT_MASK, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a530_zap.mdt", }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05040001), @@ -145,7 +147,7 @@ static const struct adreno_info a5xx_gpus[] =3D { */ .inactive_period =3D 250, .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init =3D a5xx_gpu_init, + .funcs =3D &a5xx_gpu_funcs, .zapfw =3D "a540_zap.mdt", } }; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 4a04dc43a8e6764a113d0ade3dee94bd4c0083af..56eaff2ee4e4b82b55530ac818c= 88f0d248a1942 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1691,34 +1691,6 @@ static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, s= truct msm_ringbuffer *ring) return ring->memptrs->rptr =3D gpu_read(gpu, REG_A5XX_CP_RB_RPTR); } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a5xx_hw_init, - .ucode_load =3D a5xx_ucode_load, - .pm_suspend =3D a5xx_pm_suspend, - .pm_resume =3D a5xx_pm_resume, - .recover =3D a5xx_recover, - .submit =3D a5xx_submit, - .active_ring =3D a5xx_active_ring, - .irq =3D a5xx_irq, - .destroy =3D a5xx_destroy, -#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) - .show =3D a5xx_show, -#endif -#if defined(CONFIG_DEBUG_FS) - .debugfs_init =3D a5xx_debugfs_init, -#endif - .gpu_busy =3D a5xx_gpu_busy, - .gpu_state_get =3D a5xx_gpu_state_get, - .gpu_state_put =3D a5xx_gpu_state_put, - .create_vm =3D adreno_create_vm, - .get_rptr =3D a5xx_get_rptr, - }, - .get_timestamp =3D a5xx_get_timestamp, -}; - static void check_speed_bin(struct device *dev) { struct nvmem_cell *cell; @@ -1751,7 +1723,7 @@ static void check_speed_bin(struct device *dev) devm_pm_opp_set_supported_hw(dev, &val, 1); } =20 -struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; @@ -1781,7 +1753,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) if (config->info->revn =3D=3D 510) nr_rings =3D 1; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_ri= ngs); if (ret) { a5xx_destroy(&(a5xx_gpu->base.base)); return ERR_PTR(ret); @@ -1806,3 +1778,32 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) =20 return gpu; } + +const struct adreno_gpu_funcs a5xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a5xx_hw_init, + .ucode_load =3D a5xx_ucode_load, + .pm_suspend =3D a5xx_pm_suspend, + .pm_resume =3D a5xx_pm_resume, + .recover =3D a5xx_recover, + .submit =3D a5xx_submit, + .active_ring =3D a5xx_active_ring, + .irq =3D a5xx_irq, + .destroy =3D a5xx_destroy, +#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) + .show =3D a5xx_show, +#endif +#if defined(CONFIG_DEBUG_FS) + .debugfs_init =3D a5xx_debugfs_init, +#endif + .gpu_busy =3D a5xx_gpu_busy, + .gpu_state_get =3D a5xx_gpu_state_get, + .gpu_state_put =3D a5xx_gpu_state_put, + .create_vm =3D adreno_create_vm, + .get_rptr =3D a5xx_get_rptr, + }, + .init =3D a5xx_gpu_init, + .get_timestamp =3D a5xx_get_timestamp, +}; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 44df6410bce17613702d7d04906469de4dd021b5..06dc5343e8fead56c3c95c70470= 0c1956bd0f9bf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,10 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" =20 +extern const struct adreno_gpu_funcs a6xx_gpu_funcs; +extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs; +extern const struct adreno_gpu_funcs a7xx_gpu_funcs; + static const struct adreno_reglist a612_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -683,7 +687,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D (SZ_128K + SZ_4K), .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gmuwrapper_funcs, .zapfw =3D "a610_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a612_hwcg, @@ -716,7 +720,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -747,7 +751,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -774,7 +778,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .protect =3D &a630_protect, .gmu_cgc_mode =3D 0x00000222, @@ -797,7 +801,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -822,7 +826,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .gmem =3D SZ_512K, .quirks =3D ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -847,7 +851,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a615_hwcg, @@ -873,7 +877,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a620_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a620_hwcg, @@ -896,7 +900,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a650_protect, @@ -933,7 +937,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a630_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a630_hwcg, @@ -953,7 +957,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a640_hwcg, @@ -977,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a650_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a650_hwcg, @@ -1003,7 +1007,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a660_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, @@ -1022,7 +1026,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, .protect =3D &a660_protect, @@ -1045,7 +1049,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a660_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a660_hwcg, @@ -1072,7 +1076,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_4GB_VA, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a640_hwcg, @@ -1091,7 +1095,7 @@ static const struct adreno_info a6xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gpu_funcs, .zapfw =3D "a690_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, @@ -1426,7 +1430,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_HW_APRIV, - .init =3D a6xx_gpu_init, + .funcs =3D &a6xx_gmuwrapper_funcs, .zapfw =3D "a702_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a702_hwcg, @@ -1452,7 +1456,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "a730_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a730_hwcg, @@ -1473,7 +1477,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "a740_zap.mdt", .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, @@ -1507,7 +1511,7 @@ static const struct adreno_info a7xx_gpus[] =3D { ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, @@ -1548,7 +1552,7 @@ static const struct adreno_info a7xx_gpus[] =3D { ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .protect =3D &a730_protect, @@ -1581,7 +1585,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_PREEMPTION, - .init =3D a6xx_gpu_init, + .funcs =3D &a7xx_gpu_funcs, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 4be0117c3ab1d56dc81b43ff00e3cc48b02b080f..63aa3f8205085441c7cf8d391be= facacd3aefc32 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2527,104 +2527,7 @@ static int a6xx_set_supported_hw(struct device *dev= , const struct adreno_info *i return 0; } =20 -static const struct adreno_gpu_funcs funcs =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_gmu_pm_suspend, - .pm_resume =3D a6xx_gmu_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a6xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, - .gpu_get_freq =3D a6xx_gmu_get_freq, - .gpu_set_freq =3D a6xx_gpu_set_freq, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - .sysprof_setup =3D a6xx_gmu_sysprof_setup, - }, - .get_timestamp =3D a6xx_gmu_get_timestamp, - .submit_flush =3D a6xx_flush, -}; - -static const struct adreno_gpu_funcs funcs_gmuwrapper =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_pm_suspend, - .pm_resume =3D a6xx_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a6xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - }, - .get_timestamp =3D a6xx_get_timestamp, - .submit_flush =3D a6xx_flush, -}; - -static const struct adreno_gpu_funcs funcs_a7xx =3D { - .base =3D { - .get_param =3D adreno_get_param, - .set_param =3D adreno_set_param, - .hw_init =3D a6xx_hw_init, - .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_gmu_pm_suspend, - .pm_resume =3D a6xx_gmu_pm_resume, - .recover =3D a6xx_recover, - .submit =3D a7xx_submit, - .active_ring =3D a6xx_active_ring, - .irq =3D a6xx_irq, - .destroy =3D a6xx_destroy, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .show =3D a6xx_show, -#endif - .gpu_busy =3D a6xx_gpu_busy, - .gpu_get_freq =3D a6xx_gmu_get_freq, - .gpu_set_freq =3D a6xx_gpu_set_freq, -#if defined(CONFIG_DRM_MSM_GPU_STATE) - .gpu_state_get =3D a6xx_gpu_state_get, - .gpu_state_put =3D a6xx_gpu_state_put, -#endif - .create_vm =3D a6xx_create_vm, - .create_private_vm =3D a6xx_create_private_vm, - .get_rptr =3D a6xx_get_rptr, - .progress =3D a6xx_progress, - .sysprof_setup =3D a6xx_gmu_sysprof_setup, - }, - .get_timestamp =3D a6xx_gmu_get_timestamp, - .submit_flush =3D a6xx_flush, - .feature_probe =3D a7xx_gpu_feature_probe, -}; - -struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) +static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; @@ -2635,7 +2538,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct msm_gpu *gpu; extern int enable_preemption; bool is_a7xx; - int ret; + int ret, nr_rings =3D 1; =20 a6xx_gpu =3D kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); if (!a6xx_gpu) @@ -2674,13 +2577,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); - else if (is_a7xx) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); - else if (adreno_has_gmu_wrapper(adreno_gpu)) - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); - else - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + nr_rings =3D 4; + + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_ri= ngs); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2727,3 +2626,101 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) =20 return gpu; } + +const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, + .gpu_get_freq =3D a6xx_gmu_get_freq, + .gpu_set_freq =3D a6xx_gpu_set_freq, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_gmu_get_timestamp, + .submit_flush =3D a6xx_flush, +}; + +const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_pm_suspend, + .pm_resume =3D a6xx_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_get_timestamp, + .submit_flush =3D a6xx_flush, +}; + +const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a7xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, + .gpu_get_freq =3D a6xx_gmu_get_freq, + .gpu_set_freq =3D a6xx_gpu_set_freq, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_vm =3D a6xx_create_vm, + .create_private_vm =3D a6xx_create_private_vm, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .init =3D a6xx_gpu_init, + .get_timestamp =3D a6xx_gmu_get_timestamp, + .submit_flush =3D a6xx_flush, + .feature_probe =3D a7xx_gpu_feature_probe, +}; diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 28f744f3caf7c59412aab06f912cd09a01e185ea..cb4113612b824ac49ef452bbf47= ebeda6d188366 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -235,7 +235,7 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) priv->has_cached_coherent =3D !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); =20 - gpu =3D info->init(drm); + gpu =3D info->funcs->init(drm); if (IS_ERR(gpu)) { dev_warn(drm->dev, "failed to load adreno gpu\n"); return PTR_ERR(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 5abe442637e321fb996402fd833711f0a948e176..f5e23e0022060a726377faca125= d57c7553c8493 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -71,8 +71,11 @@ enum adreno_family { (((_c) >> 8) & 0xff), \ ((_c) & 0xff) =20 +struct adreno_gpu; + struct adreno_gpu_funcs { struct msm_gpu_funcs base; + struct msm_gpu *(*init)(struct drm_device *dev); int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); void (*submit_flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int (*feature_probe)(struct msm_gpu *gpu); @@ -103,7 +106,7 @@ struct adreno_info { const char *fw[ADRENO_FW_MAX]; uint32_t gmem; u64 quirks; - struct msm_gpu *(*init)(struct drm_device *dev); + const struct adreno_gpu_funcs *funcs; const char *zapfw; u32 inactive_period; union { @@ -675,12 +678,6 @@ OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, = uint16_t cnt) OUT_RING(ring, PKT7(opcode, cnt)); } =20 -struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); -struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); -struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); -struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); -struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); - static inline uint32_t get_wptr(struct msm_ringbuffer *ring) { return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); --=20 2.51.0