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Mon, 29 Sep 2025 22:51:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGk+a6mDl8c2+qL3qeaLAv52uqJNABRBj7IAceU6HekQdYrgLtRlf003i7wMY4GUWbM+uBw7A== X-Received: by 2002:a17:90b:4c86:b0:32b:623d:ee91 with SMTP id 98e67ed59e1d1-3342a79339cmr20563742a91.27.1759211501416; Mon, 29 Sep 2025 22:51:41 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3341be23412sm19029779a91.20.2025.09.29.22.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 22:51:41 -0700 (PDT) From: Akhil P Oommen Date: Tue, 30 Sep 2025 11:18:20 +0530 Subject: [PATCH 15/17] drm/msm/adreno: Do CX GBIF config before GMU start Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-kaana-gpu-support-v1-15-73530b0700ed@oss.qualcomm.com> References: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> In-Reply-To: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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So do CX GBIF configurations before GMU wakes up. Also, move these registers to the catalog. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 12 ++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 ++++++++++------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 10 +++------- 5 files changed, 49 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index acd0ff2efde5ee9f1ccef7cf9f4d2793179a8b3b..b61354cb1eb87cbaafce92c50a4= de740f3006633 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1336,6 +1336,14 @@ static const u32 a730_protect_regs[] =3D { }; DECLARE_ADRENO_PROTECT(a730_protect, 48); =20 +static const struct adreno_reglist a730_gbif[] =3D { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 }, + { }, +}; + static const uint32_t a7xx_pwrup_reglist_regs[] =3D { REG_A6XX_UCHE_TRAP_BASE, REG_A6XX_UCHE_TRAP_BASE + 1, @@ -1463,6 +1471,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a730_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a730_gbif, .gmu_cgc_mode =3D 0x00020000, }, .preempt_record_size =3D 2860 * SZ_1K, @@ -1484,6 +1493,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a730_gbif, .gmu_chipid =3D 0x7020100, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1518,6 +1528,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, + .gbif_cx =3D a730_gbif, .gmu_chipid =3D 0x7050001, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1559,6 +1570,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, .ifpc_reglist =3D &a750_ifpc_reglist, + .gbif_cx =3D a730_gbif, .gmu_chipid =3D 0x7090100, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { @@ -1591,6 +1603,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .gbif_cx =3D a730_gbif, .gmu_chipid =3D 0x70f0000, .gmu_cgc_mode =3D 0x00020222, .bcms =3D (const struct a6xx_bcm[]) { @@ -1789,6 +1802,15 @@ static const u32 a840_protect_regs[] =3D { }; DECLARE_ADRENO_PROTECT(a840_protect, 64); =20 +static const struct adreno_reglist a840_gbif[] =3D { + { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 }, + { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 }, + { REG_A8XX_GBIF_CX_CONFIG, 0x20023000 }, + { }, +}; + static const struct adreno_info a8xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x44050a31), @@ -1807,6 +1829,7 @@ static const struct adreno_info a8xx_gpus[] =3D { .protect =3D &a840_protect, .pwrup_reglist =3D &a840_pwrup_reglist, .nonctxt_reglist =3D a840_nonctxt_regs, + .gbif_cx =3D a840_gbif, .gmu_chipid =3D 0x8020100, .bcms =3D (const struct a6xx_bcm[]) { { .name =3D "SH0", .buswidth =3D 16 }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index f24b88fb8500a2ff2aef3afa9ecd5392c67e1bac..a176c0fd2e53e48b63b44245514= 7425341309e2a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -872,7 +872,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) { struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; const struct a6xx_info *a6xx_info =3D adreno_gpu->info->a6xx; + const struct adreno_reglist *gbif_cx =3D a6xx_info->gbif_cx; u32 fence_range_lower, fence_range_upper; u32 chipid =3D 0; int ret; @@ -968,6 +970,16 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, uns= igned int state) gmu->log.iova | (gmu->log.size / SZ_4K - 1)); } =20 + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ + for (int i =3D 0; (gbif_cx && gbif_cx[i].offset); i++) + gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); + + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ + if (adreno_is_a8xx(adreno_gpu)) { + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); + } + /* Set up the lowest idle level on the GMU */ a6xx_gmu_power_config(gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 07ac5be9d0bccf4d2345eb76b08851a94187e861..e4e3e12fff952209aa831fb491b= ac42aa554b4a3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1261,17 +1261,20 @@ static int hw_init(struct msm_gpu *gpu) /* enable hardware clockgating */ a6xx_set_hwcg(gpu, true); =20 - /* VBIF/GBIF start*/ - if (adreno_is_a610_family(adreno_gpu) || - adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu) || - adreno_is_a7xx(adreno_gpu)) { + /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here= */ + if (adreno_is_a610_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, - adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); + } + + if (adreno_is_a610_family(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || + adreno_is_a650_family(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); + } else if (adreno_is_a7xx(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index a6ef8381abe5dd3eb202a645bb87a3bc352df047..e6c8b98ae16e998170d8f6eeabf= e09b4af150946 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -46,6 +46,7 @@ struct a6xx_info { const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *ifpc_reglist; + const struct adreno_reglist *gbif_cx; const struct adreno_reglist_pipe *nonctxt_reglist; u32 gmu_chipid; u32 gmu_cgc_mode; diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 9a09ce37687aba2f720637ec3845a25d72d2fff7..9675769beccf6b6b22df2a68854= 0fe826f9d2f8a 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -484,6 +484,9 @@ static int hw_init(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 + /* Increase priority of GMU traffic over GPU traffic */ + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -492,13 +495,6 @@ static int hw_init(struct msm_gpu *gpu) gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); =20 - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); - gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); - /* Make all blocks contribute to the GPU BUSY perf counter */ gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); =20 --=20 2.51.0