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Mon, 29 Sep 2025 22:51:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE5iAe3e4u5n6myqZaOqCbzZg+D9XtXMLcFkymOZGWVOgoVd1vtNUeKHmasAP52BXnr26yvmQ== X-Received: by 2002:a17:90b:548e:b0:32b:7d35:a7e6 with SMTP id 98e67ed59e1d1-3383ac467e9mr3543311a91.18.1759211463534; Mon, 29 Sep 2025 22:51:03 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3341be23412sm19029779a91.20.2025.09.29.22.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 22:51:03 -0700 (PDT) From: Akhil P Oommen Date: Tue, 30 Sep 2025 11:18:15 +0530 Subject: [PATCH 10/17] drm/msm/a6xx: Rebase GMU register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-kaana-gpu-support-v1-10-73530b0700ed@oss.qualcomm.com> References: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> In-Reply-To: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 44 +++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 +++++++++++-------= ---- 3 files changed, 172 insertions(+), 140 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index fc717c9474ca5bdd386a8e4e19f43abce10ce591..72d64eb10ca931ee90c91f7e004= 771cf6d7997a4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -585,14 +585,14 @@ static inline void pdc_write(void __iomem *ptr, u32 o= ffset, u32 value) } =20 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name); + const char *name, resource_size_t *start); =20 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct platform_device *pdev =3D to_platform_device(gmu->dev); - void __iomem *pdcptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc"); + void __iomem *pdcptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc", NULL); u32 seqmem0_drv0_reg =3D REG_A6XX_RSCC_SEQ_MEM_0_DRV0; void __iomem *seqptr =3D NULL; uint32_t pdc_address_offset; @@ -612,7 +612,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_address_offset =3D 0x30080; =20 if (!pdc_in_aop) { - seqptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); + seqptr =3D a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq", NULL); if (IS_ERR(seqptr)) goto err; } @@ -1793,7 +1793,7 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) } =20 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, - const char *name) + const char *name, resource_size_t *start) { void __iomem *ret; struct resource *res =3D platform_get_resource_byname(pdev, @@ -1810,6 +1810,9 @@ static void __iomem *a6xx_gmu_get_mmio(struct platfor= m_device *pdev, return ERR_PTR(-EINVAL); } =20 + if (start) + *start =3D res->start; + return ret; } =20 @@ -1922,7 +1925,11 @@ static int cxpd_notifier_cb(struct notifier_block *n= b, int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) { struct platform_device *pdev =3D of_find_device_by_node(node); + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -1940,12 +1947,21 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) gmu->legacy =3D true; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_mmio; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); if (IS_ERR(gmu->cxpd)) { ret =3D PTR_ERR(gmu->cxpd); @@ -1986,10 +2002,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu= , struct device_node *node) =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { + struct platform_device *pdev =3D of_find_device_by_node(node); struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; - struct platform_device *pdev =3D of_find_device_by_node(node); struct device_link *link; + resource_size_t start; + struct resource *res; int ret; =20 if (!pdev) @@ -2084,15 +2103,24 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct= device_node *node) goto err_memory; =20 /* Map the GMU registers */ - gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu", &start); if (IS_ERR(gmu->mmio)) { ret =3D PTR_ERR(gmu->mmio); goto err_memory; } =20 + res =3D platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0= _reg_memory"); + if (!res) { + ret =3D -EINVAL; + goto err_mmio; + } + + /* Identify gmu base offset from gpu base address */ + gmu->mmio_offset =3D (u32)(start - res->start); + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { - gmu->rscc =3D a6xx_gmu_get_mmio(pdev, "rscc"); + gmu->rscc =3D a6xx_gmu_get_mmio(pdev, "rscc", NULL); if (IS_ERR(gmu->rscc)) { ret =3D -ENODEV; goto err_mmio; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 06cfc294016f513a33eb4004c7892996ac9e0435..55b1c78daa8b523147435a86d6e= b629dbad18acd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -68,6 +68,7 @@ struct a6xx_gmu { struct drm_gpuvm *vm; =20 void __iomem *mmio; + u32 mmio_offset; void __iomem *rscc; =20 int hfi_irq; @@ -130,20 +131,23 @@ struct a6xx_gmu { unsigned long status; }; =20 +#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset) + static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) { - return readl(gmu->mmio + (offset << 2)); + /* The 'offset' is based on GPU's start address. Adjust it */ + return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) { - writel(value, gmu->mmio + (offset << 2)); + writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset)); } =20 static inline void gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) { - memcpy_toio(gmu->mmio + (offset << 2), data, size); + memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size); wmb(); } =20 @@ -160,17 +164,17 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u3= 2 lo, u32 hi) { u64 val; =20 - val =3D (u64) readl(gmu->mmio + (lo << 2)); - val |=3D ((u64) readl(gmu->mmio + (hi << 2)) << 32); + val =3D gmu_read(gmu, lo); + val |=3D ((u64) gmu_read(gmu, hi) << 32); =20 return val; } =20 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ - interval, timeout) + readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \ + cond, interval, timeout) #define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \ - readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \ + readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val= , cond, \ interval, timeout) =20 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index b15a242d974d6b42133171c8484d3b0413f2d3a4..09b8a0b9c0de7615f7e7e6364c1= 98405a498121a 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -40,56 +40,56 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> =20 - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + @@ -99,15 +99,15 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> - + - + - + @@ -119,71 +119,71 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -191,27 +191,27 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - - - - - + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + =20 --=20 2.51.0