From nobody Wed Dec 17 15:59:16 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F0802F747C; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=BY2E3SlIbjPyPv0BS+bFtW+XVc5mvdJKuBgR8dLe9mhB3rgo+AU4d8OU7h5SiL2m4pU/521XR1mo/hkhlcHXu8qqKluQsLD/+Rj76Z1/8XqE+uXl/MzJi2fw16OKqxv0IjMRyP9OfeeOJlKrwvNxOcY3S6w8KwsCt7UjgWB5nrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=oh4PASq7xylO3BBtX+WnDud/YQdsjyjmr7Yp6EcSjUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nDyi3Cy/axBWtyGJM6WAiJ1X3aPCezQSvPa74CrF0iz5L5MVbrRUUUOF+ubwZCBORJNsQcf/2dQWJhb5eSPolJzujkL57meOAAazAlzDxHMgeUFQxGfncGPEUEQBUerqnB7DUPu1VTDcNoAcfR/xEY6XV/YM21Pqjc5A+59BAno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OhIEuEq9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OhIEuEq9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 564B2C2BCB1; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=oh4PASq7xylO3BBtX+WnDud/YQdsjyjmr7Yp6EcSjUk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OhIEuEq9Uo8HaiLRTAhG1VFViZayJv/tQX1/2fcOPHmbqAQAYlZfzTaVsc8MueDNv P5UYWXYwZKJdCOQ+no8K3DtiLFLGq+UKe0dc0k392+qYSdOdI9z9UrDHfBnZ+1LieZ ItmfBTqbBfpBcgyMny+Nf5joVDYn3rgm/BHp3GZMfahlgcCWIhzDWEb5p89bQjPZXR tfZ0ibcXT6wz9CAVAHOt+kBENZyixG/vIGkXIEkuFO42l2WoHUaD99VtSCs3ATgxk8 QOYXWDACnQ7UKMqOIJyRM6jAmQpFruVsHeeECKWi64o+OSRuLQWrlfNrFskjzZTPIu 8lWvlmSol4G+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46E38CCA474; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:29 +0800 Subject: [PATCH 16/19] clk: amlogic: Add A5 clock peripherals controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250930-a4_a5_add_clock_driver-v1-16-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=30160; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=KeBxst5q1bZnGWsto6J1+CBIkEmgVhOABad3e1K1508=; b=CFfqtg+5M3qxmQ2Zcv522xtv3FT9zUURitpPtzBGNQ3LKfaIzcP3D9vVOvUgaDvFmdMWDKO2C R+M7D0wORm2A7gzI6PkWvafVbKlnrohqfboG2TF65zqNiO/rJF7eKu9 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller driver for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 897 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index db4b98abf4f4..eae9386d8e51 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -172,6 +172,19 @@ config COMMON_CLK_A5_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_A5_PERIPHERALS + tristate "Amlogic A5 peripherals clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + imply COMMON_CLK_A5_PLL + help + Support for the Peripherals clock controller on Amlogic A113X2 device, + AKA A5. Say Y if you want the peripherals clock to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index ff73d2486f05..15001947ba1f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-periphera= ls.o obj-$(CONFIG_COMMON_CLK_A4_PLL) +=3D a4-pll.o obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) +=3D a4-peripherals.o obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o +obj-$(CONFIG_COMMON_CLK_A5_PERIPHERALS) +=3D a5-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-peripherals.c b/drivers/clk/meson/a5-peri= pherals.c new file mode 100644 index 000000000000..eca9f3dcc256 --- /dev/null +++ b/drivers/clk/meson/a5-peripherals.c @@ -0,0 +1,883 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 Peripherals Clock Controller Driver + * + * Copyright (c) 2024-2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define DSPA_CLK_CTRL0 0x9c +#define CLK12_24_CTRL 0xa8 +#define AXI_CLK_EN0 0xac +#define TS_CLK_CTRL 0x158 +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define GEN_CLK_CTRL 0x178 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_GH_CTRL 0x18c +#define NNA_CLK_CNTL 0x220 + +static struct clk_regmap a5_rtc_dualdiv_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param a5_rtc_dualdiv_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_rtc_dualdiv =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D a5_rtc_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data a5_rtc_dualdiv_parent_data[] =3D { + { .hw =3D &a5_rtc_dualdiv.hw }, + { .hw =3D &a5_rtc_dualdiv_clkin.hw } +}; + +static struct clk_regmap a5_rtc_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_dualdiv_parent_data, + .num_parents =3D ARRAY_SIZE(a5_rtc_dualdiv_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_rtc_dualdiv_clkout =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkout", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data a5_rtc_clk_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_dualdiv_clkout.hw }, + { .fw_name =3D "pad_osc" } +}; + +static struct clk_regmap a5_rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_clk_parent_data, + .num_parents =3D ARRAY_SIZE(a5_rtc_clk_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_PCLK(_name, _reg, _bit, _pdata, _flags) \ +struct clk_regmap a5_##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D (_pdata), \ + .num_parents =3D 1, \ + .flags =3D (_flags), \ + }, \ +} + +static const struct clk_parent_data a5_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; + +#define A5_SYS_PCLK(_name, _reg, _bit, _flags) \ + A5_PCLK(_name, _reg, _bit, &a5_sys_pclk_parents, _flags) + +static A5_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); +static A5_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); +static A5_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); +static A5_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); +static A5_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); + +/* + * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that + * access the AXI bus. + */ +static A5_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); +static A5_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0); +static A5_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); +static A5_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); +static A5_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); +static A5_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0); +static A5_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); +static A5_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); +static A5_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0); +static A5_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0); +static A5_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0); +static A5_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); +static A5_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG0, 24, 0); +static A5_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0); +static A5_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); +static A5_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0); +static A5_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); +static A5_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0); +static A5_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0); +static A5_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0); +static A5_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); +static A5_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); +static A5_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); +static A5_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); +static A5_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); +static A5_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); +static A5_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); +static A5_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); +static A5_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); +static A5_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); +static A5_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); +static A5_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); +static A5_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); +static A5_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); +static A5_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); +static A5_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); +static A5_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); +static A5_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); + +static const struct clk_parent_data a5_axi_clk_parents =3D { .fw_name =3D = "axiclk" }; + +#define A5_AXI_CLK(_name, _reg, _bit, _flags) \ + A5_PCLK(_name, _reg, _bit, &a5_axi_clk_parents, _flags) + +static A5_AXI_CLK(axi_audio_vad, AXI_CLK_EN0, 0, 0); +static A5_AXI_CLK(axi_audio_top, AXI_CLK_EN0, 1, 0); +static A5_AXI_CLK(axi_ramb, AXI_CLK_EN0, 5, 0); +static A5_AXI_CLK(axi_rama, AXI_CLK_EN0, 6, 0); +static A5_AXI_CLK(axi_nna, AXI_CLK_EN0, 12, 0); + +/* + * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, + * sec_top, USB, Audio) to access the AXI bus of the DDR. + */ +static A5_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); + +/* + * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC) + * to access the AXI bus of the DDR. + */ +static A5_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); +static A5_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); + +static struct clk_regmap a5_clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected. + * + * gp1 is designed for DSU (DynamIQ Shared Unit) alone. It cannot be chang= ed + * arbitrarily. gp1 is read-only in the kernel and is only open for debug + * purposes. + */ +static u32 a5_gen_parent_table[] =3D { 0, 1, 2, 3, 6, 7, 12, 17, 19, 20, 2= 1, 22, + 23, 24, 25, 26, 27, 28}; + +static const struct clk_parent_data a5_gen_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "sysplldiv16" }, + { .fw_name =3D "ddr" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "clkmsr" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "mpll0" }, + { .fw_name =3D "mpll1" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" } +}; + +static struct clk_regmap a5_gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D a5_gen_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_gen_parent_data, + .num_parents =3D ARRAY_SIZE(a5_gen_parent_data), + }, +}; + +static struct clk_regmap a5_gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define A5_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(a5_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define A5_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(a5_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + +static const struct clk_parent_data a5_saradc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" } +}; + +static A5_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a5_saradc_parent_data); +static A5_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static A5_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); + +static const struct clk_parent_data a5_pwm_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +static A5_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static A5_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static A5_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static A5_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static A5_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static A5_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static A5_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static A5_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static A5_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static A5_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static A5_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static A5_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static A5_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static A5_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static A5_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a5_pwm_parent_data); +static A5_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static A5_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +/* + * NOTE: Channel 7 is gp1, because gp1 is designed for DSU, so spicc does = not + * support this source in the driver. + */ +static const struct clk_parent_data a5_spicc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static A5_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a5_spicc_parent_data); +static A5_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6); +static A5_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6); + +static A5_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a5_spicc_parent_data); +static A5_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6); +static A5_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22); + +static const struct clk_parent_data a5_sd_emmc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" }, + { .fw_name =3D "gp0" } +}; + +static A5_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_= data); +static A5_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); + +static A5_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_dat= a); +static A5_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); + +static struct clk_regmap a5_ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor a5_eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_125m_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Channel 6 is gp1. */ +static u32 a5_dspa_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_dspa_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "rtc" }, /* rtc_pll */ + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv4" }, + { .hw =3D &a5_rtc_clk.hw } +}; + +static struct clk_regmap a5_dspa_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D a5_dspa_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_dspa_parent_data, + .num_parents =3D ARRAY_SIZE(a5_dspa_parent_data), + }, +}; + +static struct clk_regmap a5_dspa_0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D a5_dspa_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_dspa_parent_data, + .num_parents =3D ARRAY_SIZE(a5_dspa_parent_data), + }, +}; + +static struct clk_regmap a5_dspa_1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa_1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0.hw, + &a5_dspa_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \ + MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) + +/* Channel 6 is gp1. */ +static u32 a5_nna_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_nna_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "hifi" } +}; + +static A5_COMP_SEL_WITH_TAB(nna_core, NNA_CLK_CNTL, 9, 0x7, + a5_nna_parent_data, a5_nna_parent_table); +static A5_COMP_DIV(nna_core, NNA_CLK_CNTL, 0, 7); +static A5_COMP_GATE(nna_core, NNA_CLK_CNTL, 8); + +static A5_COMP_SEL_WITH_TAB(nna_axi, NNA_CLK_CNTL, 25, 0x7, + a5_nna_parent_data, a5_nna_parent_table); +static A5_COMP_DIV(nna_axi, NNA_CLK_CNTL, 16, 7); +static A5_COMP_GATE(nna_axi, NNA_CLK_CNTL, 24); + +static struct clk_hw *a5_peripherals_hw_clks[] =3D { + [CLKID_RTC_DUALDIV_CLKIN] =3D &a5_rtc_dualdiv_clkin.hw, + [CLKID_RTC_DUALDIV] =3D &a5_rtc_dualdiv.hw, + [CLKID_RTC_DUALDIV_SEL] =3D &a5_rtc_dualdiv_sel.hw, + [CLKID_RTC_DUALDIV_CLKOUT] =3D &a5_rtc_dualdiv_clkout.hw, + [CLKID_RTC_CLK] =3D &a5_rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &a5_sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &a5_sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &a5_sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &a5_sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &a5_sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &a5_sys_dev_arb.hw, + [CLKID_SYS_MAILBOX] =3D &a5_sys_mailbox.hw, + [CLKID_SYS_JTAG_CTRL] =3D &a5_sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &a5_sys_ir_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &a5_sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &a5_sys_rom.hw, + [CLKID_SYS_CPU_ARB] =3D &a5_sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &a5_sys_rsa.hw, + [CLKID_SYS_SARADC] =3D &a5_sys_saradc.hw, + [CLKID_SYS_STARTUP] =3D &a5_sys_startup.hw, + [CLKID_SYS_SECURE] =3D &a5_sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &a5_sys_spifc.hw, + [CLKID_SYS_DSPA] =3D &a5_sys_dspa.hw, + [CLKID_SYS_NNA] =3D &a5_sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &a5_sys_eth_mac.hw, + [CLKID_SYS_RAMA] =3D &a5_sys_rama.hw, + [CLKID_SYS_RAMB] =3D &a5_sys_ramb.hw, + [CLKID_SYS_AUDIO_TOP] =3D &a5_sys_audio_top.hw, + [CLKID_SYS_AUDIO_VAD] =3D &a5_sys_audio_vad.hw, + [CLKID_SYS_USB] =3D &a5_sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &a5_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &a5_sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &a5_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &a5_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &a5_sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &a5_sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &a5_sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &a5_sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &a5_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &a5_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &a5_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &a5_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &a5_sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &a5_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &a5_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &a5_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &a5_sys_i2c_m_d.hw, + [CLKID_SYS_RTC] =3D &a5_sys_rtc.hw, + [CLKID_AXI_AUDIO_VAD] =3D &a5_axi_audio_vad.hw, + [CLKID_AXI_AUDIO_TOP] =3D &a5_axi_audio_top.hw, + [CLKID_AXI_RAMB] =3D &a5_axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &a5_axi_rama.hw, + [CLKID_AXI_NNA] =3D &a5_axi_nna.hw, + [CLKID_AXI_DEV1_DMC] =3D &a5_axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &a5_axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &a5_axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &a5_clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &a5_clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &a5_fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &a5_fclk_25m.hw, + [CLKID_GEN_SEL] =3D &a5_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a5_gen_div.hw, + [CLKID_GEN] =3D &a5_gen.hw, + [CLKID_SARADC_SEL] =3D &a5_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &a5_saradc_div.hw, + [CLKID_SARADC] =3D &a5_saradc.hw, + [CLKID_PWM_A_SEL] =3D &a5_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &a5_pwm_a_div.hw, + [CLKID_PWM_A] =3D &a5_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &a5_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &a5_pwm_b_div.hw, + [CLKID_PWM_B] =3D &a5_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &a5_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &a5_pwm_c_div.hw, + [CLKID_PWM_C] =3D &a5_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &a5_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &a5_pwm_d_div.hw, + [CLKID_PWM_D] =3D &a5_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &a5_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &a5_pwm_e_div.hw, + [CLKID_PWM_E] =3D &a5_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &a5_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &a5_pwm_f_div.hw, + [CLKID_PWM_F] =3D &a5_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &a5_pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &a5_pwm_g_div.hw, + [CLKID_PWM_G] =3D &a5_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &a5_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &a5_pwm_h_div.hw, + [CLKID_PWM_H] =3D &a5_pwm_h.hw, + [CLKID_SPICC_0_SEL] =3D &a5_spicc_0_sel.hw, + [CLKID_SPICC_0_DIV] =3D &a5_spicc_0_div.hw, + [CLKID_SPICC_0] =3D &a5_spicc_0.hw, + [CLKID_SPICC_1_SEL] =3D &a5_spicc_1_sel.hw, + [CLKID_SPICC_1_DIV] =3D &a5_spicc_1_div.hw, + [CLKID_SPICC_1] =3D &a5_spicc_1.hw, + [CLKID_SD_EMMC_A_SEL] =3D &a5_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &a5_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &a5_sd_emmc_a.hw, + [CLKID_SD_EMMC_C_SEL] =3D &a5_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &a5_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &a5_sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &a5_ts_div.hw, + [CLKID_TS] =3D &a5_ts.hw, + [CLKID_ETH_125M_DIV] =3D &a5_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &a5_eth_125m.hw, + [CLKID_ETH_RMII_DIV] =3D &a5_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &a5_eth_rmii.hw, + [CLKID_DSPA_0_SEL] =3D &a5_dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &a5_dspa_0_div.hw, + [CLKID_DSPA_0] =3D &a5_dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &a5_dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &a5_dspa_1_div.hw, + [CLKID_DSPA_1] =3D &a5_dspa_1.hw, + [CLKID_DSPA] =3D &a5_dspa.hw, + [CLKID_NNA_CORE_SEL] =3D &a5_nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &a5_nna_core_div.hw, + [CLKID_NNA_CORE] =3D &a5_nna_core.hw, + [CLKID_NNA_AXI_SEL] =3D &a5_nna_axi_sel.hw, + [CLKID_NNA_AXI_DIV] =3D &a5_nna_axi_div.hw, + [CLKID_NNA_AXI] =3D &a5_nna_axi.hw, +}; + +static const struct meson_clkc_data a5_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a5_peripherals_hw_clks), + }, +}; + +static const struct of_device_id a5_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-peripherals-clkc", + .data =3D &a5_peripherals_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_peripherals_clkc_match_table); + +static struct platform_driver a5_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-peripherals-clkc", + .of_match_table =3D a5_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a5_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0