From nobody Wed Oct 1 22:33:21 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE6D230102C for ; Mon, 29 Sep 2025 11:38:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145899; cv=none; b=hstQ35xAki7GWa6YRKEdku461m5JhrksD3ONUN/fjCgbgCKPU3zE3naVdHRbPJSgcFCsR+MSbnvW7yU1Qy/GFAZPpYh8WeR1mFFdOVN8ms0GIy5mQhMT0v7NjAkYK4fSAKyJsyCDODhUyVhxfWaB8qvaKD/iLY5iaBCABfhjQII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145899; c=relaxed/simple; bh=6sa4dBlIVtXXSWxWD+PhcdWd6PIrRysSNnN6dDj8eWM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K20guM76mKz6HoQVenF7QbmaLC+erLXc+2mJAFLkqzzJeWQ27Xqfg4RJ0yJ7qM3KqTuh3GUSv8/a4f/iuM6UZgp5GSD+OLvorYiaQKKkvb1j21WnsMZObzr56KtGWvz6Lrqr9TObnYFPVPBzVWMFn16jR7BCb/tdsAIP+dgJm4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OtGMTRWB; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OtGMTRWB" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-46e34bd8eb2so49675395e9.3 for ; Mon, 29 Sep 2025 04:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759145896; x=1759750696; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FV+6yoKv/P9OgvlWPQKcQD99p3mLWnHYMK2iXPsZM3o=; b=OtGMTRWBLoZWsgoOH2w4rn5R/b597s/xtcZj6c6DbuZnLdYiFR0M444fuo1GX1qBRb rrkA7enF54EtmAhTV+uSOr9zk1dwOb+ANiM3VbRlfP7cct59JTMMprZ3eopPpiL6JHXk W0LccJcEnBOUQzkCF1xbSCfyz7yrne7u7qWwGvXg8Q8ztmzS2/9xURXG1bV8r4jsGKuR a/7rSXjKH5rJkvZsnz0n051bIOMW/giXSXWHl6mmHxkEJb2HOkEl0TL7D95xR3+MSffD wVWgPKc0qitw1c2jaX0QjZnaNcgmSGr7A7P9N8/FNwiedtfZP64Y9uKlbyWdnwGeZ1ZA II+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759145896; x=1759750696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FV+6yoKv/P9OgvlWPQKcQD99p3mLWnHYMK2iXPsZM3o=; b=GFUHqNqcv9b51R5bTePWarfGYD797mbZm+5JzQx/yv5Y3tCOK35whC+YD5cnd8V90Z joUTwtFOkQ47bKLgtV/XCSxnr/x6ttp53IcYz578Pj1yjNWlrbPfRxvY/Earj0FlETRj G+1BFpOZ7G7iyIPv/Xx6iXeVZzu/xhimzPlEA1qh7jP/hgBT8ESAuUMO0FJTr2S4kbeJ ghXWGgjuxNZSkwrASw3w+ddwIhzeP08TcMp26bocEmqFT0gySK6YX2BU1n6L6KD+YYGN h+v/SISTrV87r77N+7rhC5MuxHqdxzS+6uxD44+lZ506JUZ+n/uZxqCTHwpI/U4fY5tZ 0Bmg== X-Forwarded-Encrypted: i=1; AJvYcCXfuQk4Jk2t/EiL8qAi+Df8SXp4Vt2uRXxqPSpvPoHNV+9KCv9X3F2fccYCyzY6kFSX9TMDweDCdjBj+bA=@vger.kernel.org X-Gm-Message-State: AOJu0YyZ6FW1c2VG7G0CAWpq07VvnQB/fKQmqC+ICcTCV0IFQOfnswnu F+7tnepemmmzuj9hdnau+ZrYyx4mj6+9BhwuVAho/gSQ8DJGxZiKDqxn X-Gm-Gg: ASbGncsvCmP3r1ThQouZZL2lUrM2ipYRpVx8hSplCcifdTDH2Ma5q5jOpo0Qv8U5UYk 1Pz+QGGh+/UMQplLGMMUoqEF4Q/xzKNDkOsETF4PkaBq+07j4W3vEEFG4ZsQWjUBpqTVRr9EdEN wRx1uEBM+ZhYG+FECf0jGtKfUXC3UjsGsJ1OAw4lHEF+Smpb+8zKWvpZ2ZFD2to+/z/CoFjNnzZ N7BuHaMqG12RxaTjG9df4Gd5LNGpGdIMLOPYElSeaadWezyjeCrnucCie8FcU+DN47if7zx6lSh F7YBjIevOtE2o3+UonGddNH63qwKFpVJNw6oHN0+7bXPvmxmJ7TbNZnv+HZrcHYYg5dmbmcMWbJ 8+t82XwqfD59I7oUVlGHUrodLN0dsXssaIX2LDQVAYOijpvDFZSfnUkP17PTIGaR254jLswezdJ +8MW4kew== X-Google-Smtp-Source: AGHT+IFI4JCC0CS5i7fI/P2/bpr7mkkJzs2jB30grNUffEVDg+ZThDdiliKzuAgxVdMuS1kcxLiNLw== X-Received: by 2002:a05:600c:3149:b0:46e:46c7:b79a with SMTP id 5b1f17b1804b1-46e46c7b979mr68799125e9.2.1759145896077; Mon, 29 Sep 2025 04:38:16 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e56f53596sm9502465e9.7.2025.09.29.04.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 04:38:15 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/5] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Date: Mon, 29 Sep 2025 13:38:00 +0200 Message-ID: <20250929113806.2484-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250929113806.2484-1-ansuelsmth@gmail.com> References: <20250929113806.2484-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The syscon compatible for the hifsys node for Mediatek MT2701/MT7623 SoC was wrongly added following the pattern of other clock node but it's actually not needed as the register are not used by other device on the SoC. On top of this it's against the schema for hifsys YAML and causes a dtbs_check warning. Drop the "syscon" compatible to mute the warning and reflect the compatible property described in the mediatek,mt2701-hifsys.yaml schema. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Christian Marangi --- arch/arm/boot/dts/mediatek/mt2701.dtsi | 2 +- arch/arm/boot/dts/mediatek/mt7623.dtsi | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/med= iatek/mt2701.dtsi index ce6a4015fed5..128b87229f3d 100644 --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -597,7 +597,7 @@ larb1: larb@16010000 { }; =20 hifsys: syscon@1a000000 { - compatible =3D "mediatek,mt2701-hifsys", "syscon"; + compatible =3D "mediatek,mt2701-hifsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/med= iatek/mt7623.dtsi index fd7a89cc337d..4b1685b93989 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -744,8 +744,7 @@ vdecsys: syscon@16000000 { =20 hifsys: syscon@1a000000 { compatible =3D "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; + "mediatek,mt2701-hifsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; --=20 2.51.0 From nobody Wed Oct 1 22:33:21 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACC53301494 for ; Mon, 29 Sep 2025 11:38:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145902; cv=none; b=HaedjjgsJToFngjYOmDsVAJG3+P8Q0Rr4nqiW+6tRvAdwyI0DSettZ8P9pyGpKdI+xkkrOyQ+tegzzTuhMrD45jkEOQz4ItEVeLufsjfbD5E4K0YDwMjZbNeZq+DQtQBPZdebdPkm3dEclsFBZJdMELeWSjmY9B/f78cCzMu6VU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145902; c=relaxed/simple; bh=uSQJLqbcal/3fIvDJghFxsrITwI7poKPi9sEc5Og8bo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rcsXErle+kIfqhZHrGZYvASgmkqbKdZUXyFytCxjdhluddxo+B8O7NVnj6UGx8lmd8PIIVKifQ2zRSvyD8PY3C5KEUnip8DNfLlnvS6nNqqohx3B9XsH0DWiEggLKVtaAXNJb6waGGjjqgf6oQGBSH0Bqj29MfWfR/WK420vddc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Is9Qdso4; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Is9Qdso4" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-46e3cdc1a6aso23314715e9.1 for ; Mon, 29 Sep 2025 04:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759145898; x=1759750698; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hYSFvNXJ1OxOrTIGf+Idmx9ir1vilL2ggeDDXDhQi4w=; b=Is9Qdso4V/OHjtjFjY+B796MGs+96wShzouCa3C6zHyNd5QVPraaN/cojktcodSrui WLS+fqxis8nVi1Ykta51n6+DEOM5AYajh7tCrUoI0bQtzKF66kMTeNCz1EbVqP6nPCBv jfAMfby07M7lvLsv9hv1W1FnQ3J2Yood6gwkatojoNnOcev1pggfotI/3jud17Zfpksp uKbU7laiSNbhTPTrc/nHFl6/s2BUZ5+HVPXzrsxmuT4vOsm2M6o4VeeSr+ABcFcvEZTw AogRhVOdAPaJ+ZIE/ny81bVm7bXJyc7BP8hR/W42ujEf2IrCWHcmTuUA5pyF9o33w7GJ tC+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759145898; x=1759750698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hYSFvNXJ1OxOrTIGf+Idmx9ir1vilL2ggeDDXDhQi4w=; b=LVjL1AJDPbYZ046YbeqkiRlCpbMH/xxR04aOUQBSNAMD3RSLL/Xb84mSWXrR+9QLoG UCDyk2P4pShl4/b2OUw9xaldP82nRMfCqPtsRzLxoqrl5ZBHzgI+AXrMH5Y24T08b0jV nyijScTRXw69lxIg0LgKxBzWwUqeWQ3YCBK5d/xboUYEsSDa4ZSgHmqeNwQj04+DajoL 4TUJYMTTjLes1zLDfBWw8Trc3FwoMTBi6wrelh/lV864QEvt0hnQbCcpLLPovr61tFbM hP2tx+kwLj2wK1ptawsAV1yZuCRu5r9vn4laJo0FRBN7LYcXysIPZOFU/vP6DE1ZdGFi KXGg== X-Forwarded-Encrypted: i=1; AJvYcCXIvLwadwu6FxdUCmobrgJk6LMm9/lYiN+G4rtdaD2rdOioWKNtiQpKaUzPK+IdNqX10mMUSuQCJmPK9fw=@vger.kernel.org X-Gm-Message-State: AOJu0YxAIiVV6yJkXOnEnlrAA6vMDQ/vGqPcVGnNNg02IYEhCpXglMzx 5Q5Bw0yOB+ymR0a57sic+qa4/H+4BZN7jItgGSD9VCIr3En9G5ljEjcn X-Gm-Gg: ASbGncvHxOOX2hZEps43CdJf3xT7IASD2p2ERIh2HkX8/OG/O4hlzwle0H9UjvtpwmJ f1BbXHo6vhQ0XGJh8Ny5TwzYYoS7NavQz57Ed017LvGAYJuLe26qMeJ90Uoiv/m4Ri2MK00vpN/ i99DipQpllKx1zurhbXGcyur31yV0t6wbRg2u/uyTIegVfAHsmi98Chl/lE+9r6S9YZOP0XR9hj VNYzwVlHdI/iCnlag8gk0H//X+VJEV9P/xZ1wd59+C5Ej49lvTyKtItfNo+zIvoXueuZDU4ZvcL maplIEhd3ClBi2V2sfpfT17qj1QzUgm302awOvsyCChj4Ajdt9Ir2wgjaSxbNSdIyGqZBot/Nea /foRT/MDBmNHvDT4lz91x4gNNYO190OZyG4TQaa4dDQ4xUKiTDYIFEMaillAz5Sr3+09CeSkEtC jmg9CkSA== X-Google-Smtp-Source: AGHT+IF6U75uQHp1Hj29+hioV51tOxwn0RQYGiAKgAy8dcq1kYp7au4JJ4UC7HyJI2gDK2knqvs2yQ== X-Received: by 2002:a05:600c:4e46:b0:45d:dbf0:4831 with SMTP id 5b1f17b1804b1-46e58a02073mr3323765e9.0.1759145897810; Mon, 29 Sep 2025 04:38:17 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e56f53596sm9502465e9.7.2025.09.29.04.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 04:38:17 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/5] dt-bindings: PCI: mediatek: Convert to YAML schema Date: Mon, 29 Sep 2025 13:38:01 +0200 Message-ID: <20250929113806.2484-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250929113806.2484-1-ansuelsmth@gmail.com> References: <20250929113806.2484-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the PCI mediatek Documentation to YAML schema to enable validation of the supported GEN1/2 Mediatek PCIe controller. While converting, lots of cleanup were done from the .txt with better specifying what is supported by the various PCIe controller variant and drop of redundant info that are part of the standard PCIe Host Bridge schema. To reduce schema complexity the .txt is split in 2 YAML, one for mt7623/mt2701 and the other for every other compatible. Signed-off-by: Christian Marangi --- .../bindings/pci/mediatek-pcie-mt7623.yaml | 164 +++++++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ---------------- .../bindings/pci/mediatek-pcie.yaml | 318 ++++++++++++++++++ 3 files changed, 482 insertions(+), 289 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7= 623.yaml delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yam= l b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml new file mode 100644 index 000000000000..e33bcc216e30 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - mediatek,mt2701-pcie + - mediatek,mt7623-pcie + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: subsys + - const: port0 + - const: port1 + - const: port2 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: free_ck + - const: sys_ck0 + - const: sys_ck1 + - const: sys_ck2 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: pcie-rst0 + - const: pcie-rst1 + - const: pcie-rst2 + + phys: + minItems: 3 + maxItems: 3 + + phy-names: + items: + - const: pcie-phy0 + - const: pcie-phy1 + - const: pcie-phy2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - resets + - reset-names + - phys + - phy-names + - power-domains + - pcie@0,0 + - pcie@1,0 + - pcie@2,0 + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + # MT7623 + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1a140000 { + compatible =3D "mediatek,mt7623-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names =3D "subsys", "port0", "port1", "port2"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0xf800 0 0 0>; + interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_L= EVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEV= EL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEV= EL_LOW>; + clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE= >, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>= , /* I/O space */ + <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; = /* memory space */ + + pcie@0,0 { + device_type =3D "pci"; + reg =3D <0x0000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@1,0 { + device_type =3D "pci"; + reg =3D <0x0800 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@2,0 { + device_type =3D "pci"; + reg =3D <0x1000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Docu= mentation/devicetree/bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 684227522267..000000000000 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,289 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - "airoha,en7523-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power do= main - which is responsible for collapsing and restoring power to the periphera= l. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622/MT7629: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port -- interrupt-names: Must include the following entries: - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received -- linux,pci-domain: PCI domain ID. Should be unique for each host controll= er - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus numb= er - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible =3D "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg =3D <0 0x1a000000 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - - pcie: pcie@1a140000 { - compatible =3D "mediatek,mt7623-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names =3D "subsys", "port0", "port1", "port2"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0xf800 0 0 0>; - interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O spa= ce */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg =3D <0x0000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@1,0 { - reg =3D <0x0800 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@2,0 { - reg =3D <0x1000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - }; - -Examples for MT2712: - - pcie1: pcie@112ff000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x112ff000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; - clock-names =3D "sys_ck1", "ahb_ck1"; - phys =3D <&u3port1 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy1"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie0: pcie@11700000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x11700000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&pericfg CLK_PERI_PCIE0>; - clock-names =3D "sys_ck0", "ahb_ck0"; - phys =3D <&u3port0 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - -Examples for MT7622: - - pcie0: pcie@1a143000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a143000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>; - clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", - "axi_ck0", "obff_ck0", "pipe_ck0"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie1: pcie@1a145000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a145000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P1_MAC_EN>, - /* designer has connect RC1 with p0_ahb clock */ - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", - "axi_ck1", "obff_ck1", "pipe_ck1"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml new file mode 100644 index 000000000000..fca6cb20d18b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-pcie + - mediatek,mt7622-pcie + - mediatek,mt7629-pcie + - items: + - const: airoha,en7523-pcie + - const: mediatek,mt7622-pcie + + reg: + maxItems: 1 + + reg-names: + enum: [ port0, port1 ] + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + interrupts: + maxItems: 1 + + interrupt-names: + const: pcie_irq + + phys: + maxItems: 1 + + phy-names: + enum: [ pcie-phy0, pcie-phy1 ] + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupts + - interrupt-names + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + + - if: + properties: + compatible: + const: mediatek,mt2712-pcie + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + minItems: 2 + maxItems: 2 + + power-domains: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + const: mediatek,mt7622-pcie + then: + properties: + clocks: + minItems: 6 + + phys: false + + phy-names: false + + required: + - power-domains + + - if: + properties: + compatible: + const: mediatek,mt7629-pcie + then: + properties: + clocks: + minItems: 6 + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: airoha,en7523-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + phys: false + + phy-names: false + + power-domain: false + +unevaluatedProperties: false + +examples: + # MT2712 + - | + #include + #include + #include + + soc_1 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@112ff000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x112ff000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ + <&pericfg>; /* CLK_PERI_PCIE1 */ + clock-names =3D "sys_ck1", "ahb_ck1"; + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy1"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x30000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@11700000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x11700000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ + <&pericfg>; /* CLK_PERI_PCIE0 */ + clock-names =3D "sys_ck0", "ahb_ck0"; + phys =3D <&u3port0 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x1000000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + # MT7622 + - | + #include + #include + #include + + soc_2 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1a143000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a143000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ + clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0_1 0>, + <0 0 0 2 &pcie_intc0_1 1>, + <0 0 0 3 &pcie_intc0_1 2>, + <0 0 0 4 &pcie_intc0_1 3>; + pcie_intc0_1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@1a145000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a145000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ + clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1_1 0>, + <0 0 0 2 &pcie_intc1_1 1>, + <0 0 0 3 &pcie_intc1_1 2>, + <0 0 0 4 &pcie_intc1_1 3>; + pcie_intc1_1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; --=20 2.51.0 From nobody Wed Oct 1 22:33:21 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B7B30170A for ; Mon, 29 Sep 2025 11:38:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145904; cv=none; b=ZIGFUMR23Fk5tolHM2I/h0zyOxp4JCkLWXDl+4AOOQQoGEzutyC4RiVj4RZvMmYQGgpjIeo1Gwg3Yp9e9iCqhN3XdauIMr+Y7dFQcgK1viirhvyeGA6qkH2xQwJsb1/MnVZPRdHmQQRZi5esCFGiLQoD/M1DjCxLzMrrD9JPgsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145904; c=relaxed/simple; bh=JmJSN/YBNM+mDU5SsW6cP009KHpjO9jA4E3c7+XHHtg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PZXaNRDqUgOY/09NPKAmHGfo+FjQiHaW273C0BTqSsnqzwOOewloh2uYxvXMT5BM05ll2nyEXkEQUDPLVmsgq7nnN0WOrLjZmBgE/QUJxYpW42/ETQcIxjFs7+KXFTBIy6yB+0dahrWNz+CDYKKKEiofwkbvv5UXT+llJzwAQn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DYN+e98o; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DYN+e98o" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-46e504975dbso8641705e9.1 for ; Mon, 29 Sep 2025 04:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759145900; x=1759750700; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=M0akVzwetHFuOLRrA1RBETtHcqSI0prdy+4IQvcPTIc=; b=DYN+e98oXyGkYzKeQVUq4kIMyWNoJyecT9cneTEE3SXYMgOpvNWiBzis72iZM3f0k8 mWiwFqdiglEAvXt8g9s/IBWZF0Ycmctu/YLqhK1+53cyo5i/6BdwELSRsM7jUQt5ZWQT WAwLs+oSHnUdDyHwbRjuq58MzksfkKmTBIo7VOscH0FDAPzY6a21raZSpjYZp2x5Tvhw OoZI8TU8Bg+yhDRIOdVpIskGn+R0F3eNcytwxPrvL89gaAbHbA6CeZSkwNYn32req/+7 y2aSAs2Cdh+1TOXrZ8S6AqwzR5ayPwmsPiH8NPAKPC/rq05G3i2PnHTCqkciZzITnUmA cPDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759145900; x=1759750700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M0akVzwetHFuOLRrA1RBETtHcqSI0prdy+4IQvcPTIc=; b=tFXbtIIRC5wkbaE1mZCsH9K7HszCba8GzYT1vOxvzQ39bU4WfbDq19Ty9imfu2bcwP WX0e1ACFQwo+P4RznSYmWVu3W7b9P1JYPrT7VxFunPfQFBDGeN1lSyMWGTR/DnGpG3om xxEAK5L0PtlUZbYyrW44jQsQfXlp6057HuKPgynEwGNwfrLkGY5DVGg0MXN7Uru2upex iPzIn56Gglj5PdgNVYDLpOXQ1POSdDZBqtjSY3Y11jpRXrvHuKBA32w/Rs1HSWA3Qlai V1Ds2FEsePDoUt1qv0rfLGS73n34ckfe/H+EGw+kVhuBcaFEMreTSkb0L/gSomh72pFT BcoQ== X-Forwarded-Encrypted: i=1; AJvYcCVXueb5JebVrqxCL8YJD3sw/hL7PmP10qHHZl5mVoyKCLuaCTReX8Uqh4BfUbRAaW1YB+QcGtuM+I/ounE=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9Sk9BRo1EL6WiJYxMVvsHA18vq+O9+G2Xmi8EIv1p93PeNh6+ 05uUi3VoEfOuzz3LXVYOzFpCaue+4W12V2524mEKHAOygJLPglFvJsc+ X-Gm-Gg: ASbGnct/MyI2CTc57/ZEOM0MeZ9W2S/m5xzLC0ABcYJGKT1e4AgAz+RPFeOoS83Di4K A6vpXu/XnNxgq/kgJ1QbHpNFCC5PKnGowNI47ffBAAJFo2wi/T+32qT8WcVVhZbqTLnAs3TmC9I 0o6qSlfupZCuvmbGYY5TPUGuzblO6rczjlffnPX3X3y+4gYSsmGTsEQb6kx9bqUUi1rIuXIyIcv X9PuNyLMGsZUTu33hINLd53YKLK9LkEaL3V4HEjxNRXxe9EE//R/72ZmysVzQnPvrKNCZZ5N/X6 ft/tgi3c9fBB2g9rpoOUwSMTObj3TIJDVVuQpwqz3bV4TFx9iXTGXb3n0QmJO46wYx+XIdtDnYM wYAEZIN/ZyoE8PBk3or2cDnoupFsqp9WDQQUjlKEzHiGwP5YLlJb9m8xtj7H9hGBBmGofJvEb97 vCpyioaA== X-Google-Smtp-Source: AGHT+IHc2sldTrNgGF8rhPUi/DYc+1Z7wh5Q8HiRuvHW/nw/mJhTW80r4LIKdvY/BzwTBOCgANZI6A== X-Received: by 2002:a05:600c:181c:b0:46d:996b:826f with SMTP id 5b1f17b1804b1-46e32a02d46mr117755925e9.25.1759145899467; Mon, 29 Sep 2025 04:38:19 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e56f53596sm9502465e9.7.2025.09.29.04.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 04:38:19 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/5] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Date: Mon, 29 Sep 2025 13:38:02 +0200 Message-ID: <20250929113806.2484-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250929113806.2484-1-ansuelsmth@gmail.com> References: <20250929113806.2484-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi --- .../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index fca6cb20d18b..b91b13a0220c 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -55,6 +56,17 @@ properties: power-domains: maxItems: 1 =20 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 =20 @@ -90,6 +102,45 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# =20 + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + reset: + maxItems: 1 + + reset-names: + const: pcie-rst1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -106,6 +157,8 @@ allOf: =20 power-domains: false =20 + mediatek,pbus-csr: false + required: - phys - phy-names @@ -123,6 +176,8 @@ allOf: =20 phy-names: false =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -135,6 +190,8 @@ allOf: clocks: minItems: 6 =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -157,6 +214,8 @@ allOf: =20 power-domain: false =20 + mediatek,pbus-csr: false + unevaluatedProperties: false =20 examples: @@ -316,3 +375,54 @@ examples: }; }; }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fa92000 { + compatible =3D "airoha,an7583-pcie"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fa92000 0x0 0x1670>; + reg-names =3D "port1"; + + clocks =3D <&scuclk EN7523_CLK_PCIE>; + clock-names =3D "sys_ck1"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy1"; + + ranges =3D <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000= >; + + resets =3D <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names =3D "pcie-rst1"; + + mediatek,pbus-csr =3D <&pbus_csr 0x8 0xc>; + + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; --=20 2.51.0 From nobody Wed Oct 1 22:33:21 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0DC73019C2 for ; Mon, 29 Sep 2025 11:38:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145905; cv=none; b=UgP9QO0jHeX7jF228ORoCT0IOpglT9I9gvuRG4tCnzDXnVivhcur+DumqjzQpXyk/Q05FwKuH3LOC/Eo+rxTkZRfz7vUpjbavTbCBEHIJndhol90t+xac3BeOwNPut47zkJQDvse4AryXmpreIQdN8W0wLAi/F05frvWcTAfW9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145905; c=relaxed/simple; bh=OuzlMBf2DYxUrGozGqCnGqXutFM3aRqod7/0oO6AhUE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MXVO2A+yUIOLkBAo3cS8ZHr1PGBXqPpkFA0PlebD8Zm/hHWgD/Mo4zJ7041coKgKRtumjLNrCcD88liYCHnqXMUBXaLOBSuvqQ2SoLZADDN6eKdjnIUrh5Z9mlM5nTzlNUyTRQaq4LGR3z1O6OHOBKPXBpk6iHlqETUA/DNb3s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cDg4tRWN; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cDg4tRWN" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-46e2826d5c6so34054575e9.1 for ; Mon, 29 Sep 2025 04:38:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759145901; x=1759750701; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3LU04oH6Jeu7LPnO6lTLYJu+6qHSNvnAGZMQiBqSTLE=; b=cDg4tRWNlagFMKq37giuUe8paoEMsdJzfqj5yqjtUm+vHz1Oyr6GKuKSVYusQ1ldqF 1fFTOG5vky8NLD6170RjsR2CG5P/5vV80nWCUoV4Xq4CXUsymPO/6ZzXSCAjxcOOFBHs z59DyiKFx0V3HlDd5Qpf09NcM0CE+v3YRzoU62VpaKtvD//L42HPF6xO+S3xhBswl6b2 sRlUL5F86XW+j2LYcdyxQx09rxTQ66Gv574PT+uarL/o/0P0pkSU09goo8lgaOcp3f4y 7HyWyg8TG2rLnzfvTYCfweg+jdd5TC0Hw9G84sRUswxo7JVg+wX0QhtF0Cq8RCkiQgvx d/Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759145901; x=1759750701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3LU04oH6Jeu7LPnO6lTLYJu+6qHSNvnAGZMQiBqSTLE=; b=aF/cYPdrajFTM/UH6zAMBI1bNc4UBQCzd7HzrU8SmnccDGMFiM+0qf4bZpZnt8zS2J d6Y/qxtPWBRohZyS9Q86RCzQKGYGBSD5E5J84HNA06DOD44clwIFemYtVYJpnPWnoB4u nEXpGUWT1T9SvRTcT/kzYbBdv3O71SWH0dnKP7vsI2R2DQuAqfH+2Evy795P5zfVP/2I O+HmcfGRFzfGrfZuk/GHvU/QQ7Za078z1CUlsVohZWIjCaf28uNviVrGj1Rc4BFCxpbQ 5YM31tylkf2sbRX2Gy+DRDzyhJTGl0vlMS4vnRzodvvmtz37FYtKlcEq5k10NVnWrdP0 nKLw== X-Forwarded-Encrypted: i=1; AJvYcCXePHFfd1KN+T+1p6ZVQeXaG29Nb+VijE81WvxkULKtwrbSk9vIDFiIDeEUYyJvzECDvNfE8FY9twbppxg=@vger.kernel.org X-Gm-Message-State: AOJu0YyCJHKf31Ssnoa+aWAsqavGJkVZuZqMuPX2XHqJZ6gdHZFRJ6TS E/3qxfS0nAO5W/9Uz2TU2nduu5gDDJ1T1iwgQZExYEDOrUDK+AftgDuVymilNw== X-Gm-Gg: ASbGncuP/Tp2eMMaSbE/4dNztdNXiEpFB1iUzYS28l+Zba3sfLUK5lBsEBXE8whm08s BPQ4nFyrBMy2rCQAiq7E8xKOJ3JkitAQuHcg/p5u/UG3+7+KtdU3JXwK22Zewf0elgMlCgMrdlZ BkOlpogkVvG9oMtP0CwdpRvMROx02nUnQ+qXWAS/dT9BRgYGJrk/I1f0Vv8RjkAqNEbKCqKPCj3 aDPZLDwLdEd2GFptNJ6ZvriA52hUBVg78zaUIhoh1G4hNiFF2/JeskfSxLSpzyzMgO9+Q0jka+J HSoYH//Wyvr3C9DmQbKbpcieTtKsHzNjL1REeJJSqpfFQoQ2mbgmva7gUAaQyjkR1tfFegYWfvz wWXW4BROt0rwbtJkSXpUusNrvMvUBchNgusnauyu7qt8DK+rg4kqLjT/S4UfsUQ4RwdUdpm8= X-Google-Smtp-Source: AGHT+IGwis8GqJEF1Qzf9bSzV6u14blzsX+OeBzCW6GOkWLJgWkwGAve2YAB0K6RDda7Irm9+euaNA== X-Received: by 2002:a05:600c:1e23:b0:46e:39e1:fc3c with SMTP id 5b1f17b1804b1-46e3a4e1b6amr123957035e9.5.1759145901122; Mon, 29 Sep 2025 04:38:21 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e56f53596sm9502465e9.7.2025.09.29.04.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 04:38:20 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/5] PCI: mediatek: convert bool to single flags entry and bitmap Date: Mon, 29 Sep 2025 13:38:03 +0200 Message-ID: <20250929113806.2484-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250929113806.2484-1-ansuelsmth@gmail.com> References: <20250929113806.2484-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To clean Mediatek SoC PCIe struct, convert all the bool to a bitmap and use a single flags to reference all the values. This permits cleaner addition of new flag without having to define a new bool in the struct. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek.c | 28 +++++++++++++++----------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 24cc30a2ab6c..1678461e56d3 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -142,24 +142,29 @@ =20 struct mtk_pcie_port; =20 +enum mtk_pcie_flags { + NEED_FIX_CLASS_ID =3D BIT(0), /* host's class ID needed to be fixed */ + NEED_FIX_DEVICE_ID =3D BIT(1), /* host's device ID needed to be fixed */ + NO_MSI =3D BIT(2), /* Bridge has no MSI support, and relies on an + * external block + */ +}; + /** * struct mtk_pcie_soc - differentiate between host generations - * @need_fix_class_id: whether this host's class ID needed to be fixed or = not - * @need_fix_device_id: whether this host's device ID needed to be fixed o= r not * @no_msi: Bridge has no MSI support, and relies on an external block * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions + * @flags: pcie device flags. */ struct mtk_pcie_soc { - bool need_fix_class_id; - bool need_fix_device_id; - bool no_msi; unsigned int device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); + u32 flags; }; =20 /** @@ -703,7 +708,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_por= t *port) writel(val, port->base + PCIE_RST_CTRL); =20 /* Set up vendor ID and class code */ - if (soc->need_fix_class_id) { + if (soc->flags & NEED_FIX_CLASS_ID) { val =3D PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); =20 @@ -711,7 +716,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_por= t *port) writew(val, port->base + PCIE_CONF_CLASS_ID); } =20 - if (soc->need_fix_device_id) + if (soc->flags & NEED_FIX_DEVICE_ID) writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); =20 /* 100ms timeout value should be enough for Gen1/2 training */ @@ -1099,7 +1104,7 @@ static int mtk_pcie_probe(struct platform_device *pde= v) =20 host->ops =3D pcie->soc->ops; host->sysdata =3D pcie; - host->msi_domain =3D pcie->soc->no_msi; + host->msi_domain =3D !!(pcie->soc->flags & NO_MSI); =20 err =3D pci_host_probe(host); if (err) @@ -1187,9 +1192,9 @@ static const struct dev_pm_ops mtk_pcie_pm_ops =3D { }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_v1 =3D { - .no_msi =3D true, .ops =3D &mtk_pcie_ops, .startup =3D mtk_pcie_startup_port, + .flags =3D NO_MSI, }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 =3D { @@ -1199,19 +1204,18 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt271= 2 =3D { }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 =3D { - .need_fix_class_id =3D true, .ops =3D &mtk_pcie_ops_v2, .startup =3D mtk_pcie_startup_port_v2, .setup_irq =3D mtk_pcie_setup_irq, + .flags =3D NEED_FIX_CLASS_ID, }; =20 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { - .need_fix_class_id =3D true, - .need_fix_device_id =3D true, .device_id =3D PCI_DEVICE_ID_MEDIATEK_7629, .ops =3D &mtk_pcie_ops_v2, .startup =3D mtk_pcie_startup_port_v2, .setup_irq =3D mtk_pcie_setup_irq, + .flags =3D NEED_FIX_CLASS_ID | NEED_FIX_DEVICE_ID, }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { --=20 2.51.0 From nobody Wed Oct 1 22:33:21 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61183019D1 for ; Mon, 29 Sep 2025 11:38:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145906; cv=none; b=GDK+KwsEOlA3OjC4t+58J0iMAFYli/gxF5RS+RAhDGWaUB4DXCp6DYq1UuDML6w5iKooqKHwTX0fx30wb2H7ahOJH91af2bAo3wqW2dEUVtbSx/EdPK0QKSJo8nfIpcU0zdsAi15xKkX68q7FOySRZlFDBfjT1X5uriZipm9lAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759145906; c=relaxed/simple; bh=Y9B4pzLzBUoQ9UIuQ9tIIiCjBmPz1CktqXuCtCWM/sI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jXfZUDbS7VsSnV2MLCbxnLuAmaBvm3rMx/bKSeXJEZp9KpmF9XlUSHCjAkrjCBIXPC6GeULF2Rc22oXAtiBzZrz/EpwWv3tPakON+V6MdvnRX4Xsm2f0Y1QklXsONb+gjyqF8JgbytjBgAbUgKAptB0ehMm0F7UXm7Pftjw9/6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PgLlWE2V; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PgLlWE2V" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-46e52279279so6864485e9.3 for ; Mon, 29 Sep 2025 04:38:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759145903; x=1759750703; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HfCCKZmM8pHKKYsT+xDhYQD00mwQ4CthcxXjlQ/ajbw=; b=PgLlWE2VVDs5gVdfQme1SED6pFSZ8LG0i6DrTeojYnEV2/WzX9F9nb7eWeQGPPRA7d B+hFkECQ0al2qeu4K87WXDcus1xHYXkDZ5RNVcLXb2cqSRtWs+6oIR1k4fpNfYRJhLP6 q10p3PGwqD/tW6fYr3EjNpFikq+tegwarDwDKaYR0aDiHFD9e25AljUj4C3l4uHzwCku XB655er/hfGG6E37RqLafMqbJY+dkydMEqzR4E6RXHE+u+VcpUEfTkB6C0gKOZdvqgto ovY7cN6nlwRu/+fTPicbaDwe0X6DPrWb6/uekD2dj736US8mNEhFAg9FqlldV2sf9ZiF 8wfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759145903; x=1759750703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HfCCKZmM8pHKKYsT+xDhYQD00mwQ4CthcxXjlQ/ajbw=; b=NQZFKPU3ERDbZTOr2Ur4ubURhFjZxKXF6+bqFCApvpK9IUpoP3OwFuZgfp2uPxLmbF ietZUoxBFwwuTgKH0bFos/NXgw6w5cqM1vsph/eg/3tQPZHOi4cMpxzfNyiOWq5FUDnW ytZlPcSCL3xaWgfwE8Xau3Gkm/m5tUY9zA7eLwaPsSe+EsiygaizDw5uT0kpTNLZE6Xq WwA1eiPTwRwyFsxcebNQPItfGK60AcIN6GISNJArcjdtSD8O+mKrpt/l8mCGsZseWCOb x7yQSMhBfrf7iBoaSupHjerZs5+aK5LwNVIf07s0nc/ffKBLd68eOFsXcSu5N9yAIoB9 KBkA== X-Forwarded-Encrypted: i=1; AJvYcCXMFtBtqJu8h5jhS2h+tGPPQdMHjphBPf1u1j7+EawSXkTUBtP5lPRkPZVgq+Z7nmRXTPxp0pK9yMWKbTk=@vger.kernel.org X-Gm-Message-State: AOJu0YwqEZ+cmN7TcIfoDHonowkentBxRe1rJ5oswAgEi1r0yQfwa3BX XlBGkwKDrIPcpPxewZ5i1basOgxO6a04RIQeA8wUx0nwsToVw3eakqxP X-Gm-Gg: ASbGncuRlS/1Df7yjN44ktx1NxwCvTWnQMksqHT7y6Z3idLEPu1GtfOKurlGUA1oHDA CwyTYqKLWtAaU3WH8iX/TvIMwHIucItJYEfCZZqTQqWbxSYEZlTlKxHSCp3BGjlDjbum6eCGiLy 6zq/ESzEO4pAAzC5pMxGiCKl0nRiIScZg4deTdyL+5kI1MM0R4U2bsiq2YBJkXUURIWSsquQe/G GePuxa803KYGRLd/Gk2cJHOSCTj11ZdEJqGoV4Adnz5hMmQKKgk3WaPv+7QI3cBJXPRnT3cvAal FomY2a2DyMuWi+74rAR9GOnamXKCSA8sJlN+CmU1TXkXKW0/7/tr1/yVFjDyVD/QDawZ1ukCVDG bW0FnvKo4qCBjf95UEs8VervWhnK0PwQfzQ5PluLL3H1USoRYEiyTZWjX/ZLVzW3oO2kqWKw8uW o8227CgQ== X-Google-Smtp-Source: AGHT+IHyG6lnL8qQ0LD131D8WPiKwUrMMhMJ4PKeOnuBD/ytBbwWaTjIucbfk9dUwJTA+msn8KI/1A== X-Received: by 2002:a05:600c:608d:b0:46e:4f25:aace with SMTP id 5b1f17b1804b1-46e510d28edmr38669385e9.6.1759145902845; Mon, 29 Sep 2025 04:38:22 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-46e56f53596sm9502465e9.7.2025.09.29.04.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 04:38:22 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 5/5] PCI: mediatek: add support for Airoha AN7583 SoC Date: Mon, 29 Sep 2025 13:38:04 +0200 Message-ID: <20250929113806.2484-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250929113806.2484-1-ansuelsmth@gmail.com> References: <20250929113806.2484-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the second PCIe Root Complex present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new flag to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. While at it, also add additional info on the PERST# Signal delay comments and use dedicated macro. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek.c | 92 ++++++++++++++++++++------ 1 file changed, 70 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 1678461e56d3..3340c005da4b 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -148,6 +148,7 @@ enum mtk_pcie_flags { NO_MSI =3D BIT(2), /* Bridge has no MSI support, and relies on an * external block */ + SKIP_PCIE_RSTB =3D BIT(3), /* Skip calling RSTB bits on PCIe probe */ }; =20 /** @@ -684,28 +685,32 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } =20 - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); - - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); - - /* - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should - * be delayed 100ms (TPVPERL) for the power and clock to become stable. - */ - msleep(100); - - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val =3D readl(port->base + PCIE_RST_CTRL); - val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + if (!(soc->flags & SKIP_PCIE_RSTB)) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from + * link up to link down, this will reset MAC control registers + * and configuration space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification revision 3.0 sections + * 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } =20 /* Set up vendor ID and class code */ if (soc->flags & NEED_FIX_CLASS_ID) { @@ -826,6 +831,41 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port = *port) return 0; } =20 +static int mtk_pcie_startup_port_an7583(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct device *dev =3D pcie->dev; + struct pci_host_bridge *host; + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow + * the hw to detect if a given address is accessible on PCIe + * controller. + */ + pbus_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + host =3D pci_host_bridge_from_priv(pcie); + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr =3D entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size =3D lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + + return mtk_pcie_startup_port_v2(port); +} + static void mtk_pcie_enable_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie =3D port->pcie; @@ -1210,6 +1250,13 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622= =3D { .flags =3D NEED_FIX_CLASS_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_an7583, + .setup_irq =3D mtk_pcie_setup_irq, + .flags =3D NEED_FIX_CLASS_ID | SKIP_PCIE_RSTB, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { .device_id =3D PCI_DEVICE_ID_MEDIATEK_7629, .ops =3D &mtk_pcie_ops_v2, @@ -1219,6 +1266,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = =3D { }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { + { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.51.0