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charset="utf-8" From: Sachin Gupta Document the 'dll-hsr-list' property for MMC device tree bindings. The 'dll-hsr-list' property defines the DLL configurations for HS400 and HS200 modes. QC SoCs can have 0 to 4 SDHCI instances, and each one may need different tuning. Signed-off-by: Sachin Gupta Signed-off-by: Ram Prakash Gupta --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 22d1f50c3fd1..a60222473990 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -137,6 +137,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. =20 + qcom,dll-hsr-list: + maxItems: 10 + $ref: /schemas/types.yaml#/definitions/uint32-array + description: platform specific settings for DLL registers. + iommus: minItems: 1 maxItems: 8 --=20 2.34.1 From nobody Wed Oct 1 22:37:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B76973009D8; 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charset="utf-8" From: Sachin Gupta Add the core_major and core_minor variables to the msm_host structure, allowing these variables to be accessed more easily throughout the msm_host context. This update is necessary for an upcoming follow-up patch. Signed-off-by: Sachin Gupta Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 9d8e20dc8ca1..36700735aa3e 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -282,6 +282,8 @@ struct sdhci_msm_host { bool tuning_done; bool calibration_done; u8 saved_tuning_phase; + u8 core_major; + u16 core_minor; bool use_cdclp533; u32 curr_pwr_state; u32 curr_io_level; @@ -2673,6 +2675,10 @@ static int sdhci_msm_probe(struct platform_device *p= dev) core_major =3D (core_version & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT; core_minor =3D core_version & CORE_VERSION_MINOR_MASK; + + msm_host->core_major =3D core_major; + msm_host->core_minor =3D core_minor; + dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", core_version, core_major, core_minor); =20 --=20 2.34.1 From nobody Wed Oct 1 22:37:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B761D3009D5; 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charset="utf-8" From: Sachin Gupta This update introduces the capability to configure HS200 and HS400 DLL settings via the device tree and parsing it. Signed-off-by: Sachin Gupta Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 91 ++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 36700735aa3e..d07f0105b733 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -265,6 +265,19 @@ struct sdhci_msm_variant_info { const struct sdhci_msm_offset *offset; }; =20 +/* + * DLL registers which needs be programmed with HSR settings. + * Add any new register only at the end and don't change the + * sequence. + */ +struct sdhci_msm_dll { + u32 dll_config[2]; + u32 dll_config_2[2]; + u32 dll_config_3[2]; + u32 dll_usr_ctl[2]; + u32 ddr_config[2]; +}; + struct sdhci_msm_host { struct platform_device *pdev; void __iomem *core_mem; /* MSM SDCC mapped address */ @@ -273,6 +286,7 @@ struct sdhci_msm_host { struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ /* core, iface, cal and sleep clocks */ struct clk_bulk_data bulk_clks[4]; + struct sdhci_msm_dll dll; #ifdef CONFIG_MMC_CRYPTO struct qcom_ice *ice; #endif @@ -301,6 +315,7 @@ struct sdhci_msm_host { u32 dll_config; u32 ddr_config; bool vqmmc_enabled; + bool artanis_dll; }; =20 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_h= ost *host) @@ -2516,6 +2531,73 @@ static int sdhci_msm_gcc_reset(struct device *dev, s= truct sdhci_host *host) return ret; } =20 +static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_nam= e, + u32 **dll_table, int *len) +{ + struct device_node *np =3D dev->of_node; + u32 *arr =3D NULL; + int ret =3D 0, sz =3D 0; + + if (!np) + return -ENODEV; + if (!of_get_property(np, prop_name, &sz)) + return -EINVAL; + + sz =3D sz / sizeof(*arr); + if (sz <=3D 0) + return -EINVAL; + + arr =3D kcalloc(sz, sizeof(*arr), GFP_KERNEL); + if (!arr) + return -ENOMEM; + + ret =3D of_property_read_u32_array(np, prop_name, arr, sz); + if (ret) { + dev_err(dev, "%s failed reading array %d\n", prop_name, ret); + *len =3D 0; + return ret; + } + + *dll_table =3D arr; + *len =3D sz; + + return ret; +} + +static int sdhci_msm_dt_parse_dll_info(struct device *dev, struct sdhci_ms= m_host *msm_host) +{ + int dll_table_len, dll_reg_count; + u32 *dll_table =3D NULL; + int i, j; + + msm_host->artanis_dll =3D false; + + if (sdhci_msm_dt_get_array(dev, "qcom,dll-hsr-list", + &dll_table, &dll_table_len)) + return -EINVAL; + + dll_reg_count =3D sizeof(struct sdhci_msm_dll) / sizeof(u32); + + if (dll_table_len !=3D dll_reg_count) { + dev_err(dev, "Number of HSR entries are not matching\n"); + return -EINVAL; + } + + for (i =3D 0, j =3D 0; j < 2; i =3D i + 5, j++) { + msm_host->dll.dll_config[j] =3D dll_table[i]; + msm_host->dll.dll_config_2[j] =3D dll_table[i + 1]; + msm_host->dll.dll_config_3[j] =3D dll_table[i + 2]; + msm_host->dll.dll_usr_ctl[j] =3D dll_table[i + 3]; + msm_host->dll.ddr_config[j] =3D dll_table[i + 4]; + } + + msm_host->artanis_dll =3D true; + + kfree(dll_table); + + return 0; +} + static int sdhci_msm_probe(struct platform_device *pdev) { struct sdhci_host *host; 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charset="utf-8" From: Sachin Gupta With the current DLL sequence stability issues for data transfer seen in HS400 and HS200 modes. "mmc0: cqhci: error IRQ status: 0x00000000 cmd error -84 data error 0" Rectify the DLL programming sequence as per latest hardware programming guide Signed-off-by: Sachin Gupta Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 271 ++++++++++++++++++++++++++++++++--- 1 file changed, 252 insertions(+), 19 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index d07f0105b733..0f60a3655ef1 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -28,6 +28,7 @@ #define CORE_VERSION_MAJOR_SHIFT 28 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) #define CORE_VERSION_MINOR_MASK 0xff +#define SDHCI_MSM_MIN_V_7FF 0x6e =20 #define CORE_MCI_GENERICS 0x70 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) @@ -118,7 +119,8 @@ #define CORE_PWRSAVE_DLL BIT(3) =20 #define DDR_CONFIG_POR_VAL 0x80040873 - +#define DLL_CONFIG_3_POR_VAL 0x10 +#define TCXO_FREQ 19200000 =20 #define INVALID_TUNING_PHASE -1 #define SDHCI_MSM_MIN_CLOCK 400000 @@ -318,6 +320,16 @@ struct sdhci_msm_host { bool artanis_dll; }; =20 +enum dll_init_context { + DLL_INIT_NORMAL, + DLL_INIT_FROM_CX_COLLAPSE_EXIT, +}; + +enum mode { + HS400, // equivalent to SDR104 mode for DLL. + HS200, // equivalent to SDR50 mode for DLL. +}; + static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_h= ost *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -802,6 +814,208 @@ static int msm_init_cm_dll(struct sdhci_host *host) return 0; } =20 +static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) +{ + return SDHCI_MSM_MIN_CLOCK; +} + +static unsigned int sdhci_msm_get_clk_rate(struct sdhci_host *host, u32 re= q_clk) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct clk *core_clk =3D msm_host->bulk_clks[0].clk; + struct mmc_ios ios =3D host->mmc->ios; + unsigned int sup_clk; + + if (req_clk < sdhci_msm_get_min_clock(host)) + return sdhci_msm_get_min_clock(host); + + sup_clk =3D clk_get_rate(core_clk); + + if (ios.timing =3D=3D MMC_TIMING_MMC_HS400 || + host->flags & SDHCI_HS400_TUNING) + sup_clk =3D sup_clk / 2; + + return sup_clk; +} + +/* Initialize the DLL (Programmable Delay Line) */ +static int sdhci_msm_configure_dll(struct sdhci_host *host, enum dll_init_= context + init_context, enum mode index) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; + struct mmc_host *mmc =3D host->mmc; + u32 ddr_cfg_offset, core_vendor_spec, config; + void __iomem *ioaddr =3D host->ioaddr; + unsigned long flags, dll_clock; + int rc =3D 0, wait_cnt =3D 50; + + dll_clock =3D sdhci_msm_get_clk_rate(host, host->clock); + spin_lock_irqsave(&host->lock, flags); + + core_vendor_spec =3D readl_relaxed(ioaddr + msm_offset->core_vendor_spec); + + /* + * Always disable PWRSAVE during the DLL power + * up regardless of its current setting. + */ + core_vendor_spec &=3D ~CORE_CLK_PWRSAVE; + writel_relaxed(core_vendor_spec, ioaddr + msm_offset->core_vendor_spec); + + if (msm_host->use_14lpp_dll_reset) { + /* Disable CK_OUT */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config &=3D ~CORE_CK_OUT_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Disable the DLL clock */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config |=3D CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + + /* + * Write 1 to DLL_RST bit of DLL_CONFIG register + * and Write 1 to DLL_PDN bit of DLL_CONFIG register. + */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config |=3D (CORE_DLL_RST | CORE_DLL_PDN); + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Configure DLL_CONFIG_3 and USER_CTRL + * (Only applicable for 7FF projects). + */ + if (msm_host->core_minor >=3D SDHCI_MSM_MIN_V_7FF) { + writel_relaxed(msm_host->dll.dll_config_3[index], + ioaddr + msm_offset->core_dll_config_3); + writel_relaxed(msm_host->dll.dll_usr_ctl[index], + ioaddr + msm_offset->core_dll_usr_ctl); + } + + /* + * Set DDR_CONFIG since step 7 is setting TEST_CTRL that can be skipped. + */ + ddr_cfg_offset =3D msm_host->updated_ddr_cfg ? msm_offset->core_ddr_config + : msm_offset->core_ddr_config_old; + + config =3D msm_host->dll.ddr_config[index]; + writel_relaxed(config, ioaddr + ddr_cfg_offset); + + /* Set DLL_CONFIG_2 */ + if (msm_host->use_14lpp_dll_reset) { + u32 mclk_freq; + int cycle_cnt; + + /* + * Only configure the mclk_freq in normal DLL init + * context. If the DLL init is coming from + * CX Collapse Exit context, the host->clock may be zero. + * The DLL_CONFIG_2 register has already been restored to + * proper value prior to getting here. + */ + if (init_context =3D=3D DLL_INIT_NORMAL) { + cycle_cnt =3D readl_relaxed(ioaddr + + msm_offset->core_dll_config_2) + & CORE_FLL_CYCLE_CNT ? 8 : 4; + + mclk_freq =3D DIV_ROUND_CLOSEST_ULL(dll_clock * cycle_cnt, TCXO_FREQ); + + if (dll_clock < 100000000) { + pr_err("%s: %s: Non standard clk freq =3D%u\n", + mmc_hostname(mmc), __func__, dll_clock); + rc =3D -EINVAL; + goto out; + } + + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config =3D (config & ~GENMASK(17, 10)) | + FIELD_PREP(GENMASK(17, 10), mclk_freq); + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + /* wait for 5us before enabling DLL clock */ + udelay(5); + } + + config =3D msm_host->dll.dll_config[index]; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Wait for 52us */ + spin_unlock_irqrestore(&host->lock, flags); + usleep_range(60, 70); + spin_lock_irqsave(&host->lock, flags); + + /* + * Write 0 to DLL_RST bit of DLL_CONFIG register + * and Write 0 to DLL_PDN bit of DLL_CONFIG register. + */ + config &=3D ~CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + config &=3D ~CORE_DLL_PDN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + /* Write 1 to DLL_RST bit of DLL_CONFIG register */ + config |=3D CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Write 0 to DLL_RST bit of DLL_CONFIG register */ + config &=3D ~CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Set CORE_DLL_CLOCK_DISABLE to 0 */ + if (msm_host->use_14lpp_dll_reset) { + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config &=3D ~CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + + /* Set DLL_EN bit to 1. */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config |=3D CORE_DLL_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Wait for 8000 input clock. Here we calculate the + * delay from fixed clock freq 192MHz, which turns out 42us. + */ + spin_unlock_irqrestore(&host->lock, flags); + usleep_range(50, 60); + spin_lock_irqsave(&host->lock, flags); + + /* Set CK_OUT_EN bit to 1. */ + config |=3D CORE_CK_OUT_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Wait until DLL_LOCK bit of DLL_STATUS register + * becomes '1'. + */ + while (!(readl_relaxed(ioaddr + msm_offset->core_dll_status) & + CORE_DLL_LOCK)) { + /* max. wait for 50us sec for LOCK bit to be set */ + if (--wait_cnt =3D=3D 0) { + dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", + mmc_hostname(mmc)); + rc =3D -ETIMEDOUT; + goto out; + } + /* wait for 1us before polling again */ + udelay(1); + } + +out: + if (core_vendor_spec & CORE_CLK_PWRSAVE) { + /* Reenable PWRSAVE as needed */ + config =3D readl_relaxed(ioaddr + msm_offset->core_vendor_spec); + config |=3D CORE_CLK_PWRSAVE; + writel_relaxed(config, ioaddr + msm_offset->core_vendor_spec); + } + spin_unlock_irqrestore(&host->lock, flags); + return rc; +} + static void msm_hc_select_default(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -924,14 +1138,31 @@ static void sdhci_msm_hc_select_mode(struct sdhci_ho= st *host) msm_hc_select_default(host); } =20 +static int sdhci_msm_init_dll(struct sdhci_host *host, enum dll_init_conte= xt init_context) +{ + if (host->mmc->ios.timing =3D=3D MMC_TIMING_UHS_SDR104 || + host->mmc->ios.timing =3D=3D MMC_TIMING_MMC_HS400) + return sdhci_msm_configure_dll(host, init_context, HS400); + + return sdhci_msm_configure_dll(host, init_context, HS200); +} + +static int sdhci_msm_dll_config(struct sdhci_host *host, enum dll_init_con= text init_context) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + + return msm_host->artanis_dll ? sdhci_msm_init_dll(host, init_context) : + msm_init_cm_dll(host); +} + static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; u32 config, calib_done; int ret; - const struct sdhci_msm_offset *msm_offset =3D - msm_host->offset; =20 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); =20 @@ -939,7 +1170,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci= _host *host) * Retuning in HS400 (DDR mode) will fail, just reset the * tuning block and restore the saved tuning phase. */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); if (ret) goto out; =20 @@ -1027,7 +1258,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhc= i_host *host) return ret; } =20 -static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) +static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host, enum= mode index) { struct mmc_host *mmc =3D host->mmc; u32 dll_status, config, ddr_cfg_offset; @@ -1050,7 +1281,11 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct = sdhci_host *host) ddr_cfg_offset =3D msm_offset->core_ddr_config; else ddr_cfg_offset =3D msm_offset->core_ddr_config_old; - writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); + + if (msm_host->artanis_dll) + writel_relaxed(msm_host->dll.ddr_config[index], host->ioaddr + ddr_cfg_o= ffset); + else + writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); =20 if (mmc->ios.enhanced_strobe) { config =3D readl_relaxed(host->ioaddr + @@ -1107,11 +1342,10 @@ static int sdhci_msm_hs400_dll_calibration(struct s= dhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; struct mmc_host *mmc =3D host->mmc; - int ret; u32 config; - const struct sdhci_msm_offset *msm_offset =3D - msm_host->offset; + int ret; =20 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); =20 @@ -1119,7 +1353,8 @@ static int sdhci_msm_hs400_dll_calibration(struct sdh= ci_host *host) * Retuning in HS400 (DDR mode) will fail, just reset the * tuning block and restore the saved tuning phase. */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); + if (ret) goto out; =20 @@ -1139,7 +1374,7 @@ static int sdhci_msm_hs400_dll_calibration(struct sdh= ci_host *host) if (msm_host->use_cdclp533) ret =3D sdhci_msm_cdclp533_calibration(host); else - ret =3D sdhci_msm_cm_dll_sdc4_calibration(host); + ret =3D sdhci_msm_cm_dll_sdc4_calibration(host, HS400); out: pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), __func__, ret); @@ -1178,7 +1413,8 @@ static int sdhci_msm_restore_sdr_dll_config(struct sd= hci_host *host) return 0; =20 /* Reset the tuning block */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); + if (ret) return ret; =20 @@ -1242,12 +1478,11 @@ static int sdhci_msm_execute_tuning(struct mmc_host= *mmc, u32 opcode) if (host->flags & SDHCI_HS400_TUNING) { sdhci_msm_hc_select_mode(host); msm_set_clock_rate_for_bus_mode(host, ios.clock); - host->flags &=3D ~SDHCI_HS400_TUNING; } =20 retry: /* First of all reset the tuning block */ - rc =3D msm_init_cm_dll(host); + rc =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); if (rc) return rc; =20 @@ -1310,6 +1545,9 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) rc =3D -EIO; } =20 + if (host->flags & SDHCI_HS400_TUNING) + host->flags &=3D ~SDHCI_HS400_TUNING; + if (!rc) msm_host->tuning_done =3D true; return rc; @@ -1830,11 +2068,6 @@ static unsigned int sdhci_msm_get_max_clock(struct s= dhci_host *host) return clk_round_rate(core_clk, ULONG_MAX); } =20 -static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) -{ - return SDHCI_MSM_MIN_CLOCK; -} - /* * __sdhci_msm_set_clock - sdhci_msm clock control. * --=20 2.34.1