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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH V2 1/4] dt-bindings: dma: Update ADMA bindings for tegra264 Date: Mon, 29 Sep 2025 16:29:27 +0530 Message-ID: <20250929105930.1767294-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250929105930.1767294-1-sheetal@nvidia.com> References: <20250929105930.1767294-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|MW5PR12MB5598:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c11c309-0a14-4942-08f1-08ddff47a6a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZMcLJUPUH4dHidro3U+Iu5W6dKSQQE8WN8pl6RmJgHJHv1rEnGetoJDRJQWU?= =?us-ascii?Q?uHeKCMrNiaS18MLVk48/CcA9l7CqntmuymZuzJTt/yD0KSHxateGdYYnvQXa?= =?us-ascii?Q?aBNZqvirWuu4+Ge8ejoLB1AdK7ccoK6czAwBQFPCEf/f0EZcBegiTjZWJ14I?= =?us-ascii?Q?dkuQR52Zp35/KebvwbJEsOclyFxLE4I9NIWjcJtIX3FcRHGHHErhtQCVlbqe?= =?us-ascii?Q?qZyJudxaUi9zA6vYUru6r6s30SjZ+/iuMXbbfeet0Ctu+TbmdQxwJxNRziSY?= =?us-ascii?Q?GavWgyc5WckgpwdbSeBfahlBkZ/yCdzgBkyxelulWMfc9JHiyYwSo7PoZcTn?= =?us-ascii?Q?pQNCespilJIWElrnt9Rja9Sa87oIKXWwJEBwKLSI4aZj80T5eG6WlN1ovFHa?= =?us-ascii?Q?jRiTiikakV04tvQj6qZMEaZZkJhVvt5cF2/BqPdGUSr32Sa7vCrNAcu7MFYF?= =?us-ascii?Q?hbQm6eMv6TTB4/QPw6uJXBIqYRItD5nMerHulMh0KZfYT0hWJS7gwq+AIrma?= =?us-ascii?Q?+bOKa+qUbIJ8OBZqNzyx5k+KHM6iU40MpQtdD9F3wT0dworaCfy6nn0zRVhi?= =?us-ascii?Q?EjTsrHnppOOah8CMuuHmMo+GNiS7ya5RbwL4ZP01hpnV3p/xs+yoFFmhmteJ?= =?us-ascii?Q?jkkmuIcqOUs1GZ73zbVy4CD2TIr/+g7CSgV06Mx9oXshkHFFVelhJ7X1wYa0?= =?us-ascii?Q?Q6RESz+Zpl32pPyPXEdzLrQE6CVsZh5sI6ZIz6wDgZRS8VcRAlTi5sTplpBZ?= =?us-ascii?Q?1cQ2AyIh/mJmK4sj22pwx+KPJ/P7tNfju6g/6GGh6gCJKLp2M6CmRb4oR0Ig?= =?us-ascii?Q?sQZq2+rTGiHQ8J3AHQZemjvANaCPPXNfhmaUOetUi6tw6I80NPXEp13gm5gV?= =?us-ascii?Q?d0T5QroHZjTsjcdnoMq39piiFCmOaSMubce4LbKGM3SyWsnRCE8A8pnMVXY+?= =?us-ascii?Q?xrO5GSwtwjgDCtAmdQJsWKf2XVoGPkFqD50fBJSBSjGbCTT8Cwv+jHnbxISk?= =?us-ascii?Q?4p9Ogs3im/q3Iq9EL9XGQ+hCh4qUOzUeaRfn/SP9872HFaIRwGlA+xEefAps?= =?us-ascii?Q?YbhFBAXggFrrw1eEgyhnYSc7SFQWRyHVh/+zuHVPb4SCHSdeaK+TeOupMiCQ?= =?us-ascii?Q?BkWfGTuyUxdf/FqNX05yjNiOhI+exKUpZogFrPpWdYAJvHNRFWi+oFyesOsw?= =?us-ascii?Q?eyn9cz019atf7ViX8/3174RC0AVETPY54dY5A4RMiuGZkERGYD6GEplEn7Tl?= =?us-ascii?Q?TwhUEn02wSH9d8R2fH76eA+yShMArGerhkiZTp3Wv3AoUAOuvY8+E2Fewemr?= =?us-ascii?Q?6EWm7h0ZXcww3ZmcMJGGl+Hr2VZfbww020W+4FfeMgv4xegpISgwnjlqQtcJ?= =?us-ascii?Q?hIwi4TAHWvr2I/mOHhUT7yLgiVV7v6IItn+CdKRsJ2mSzpDIiTg6OBQGIUtQ?= =?us-ascii?Q?3yGywcxGEVT+m+fMsg1EZ1fV6YaIBA22j+D2J0WdoWe/c0YrRqNHB9PXttQ9?= =?us-ascii?Q?3TYsrft7WKr/VwyFRvKm+b+EEDAT/q0F2KRFzkWBAVXeNTYbili5wR0C3O6Q?= =?us-ascii?Q?5zTkuoC9l+d7jFC70Gw=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2025 11:02:15.9071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c11c309-0a14-4942-08f1-08ddff47a6a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5598 Content-Type: text/plain; charset="utf-8" From: sheetal - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal Reviewed-by: Rob Herring (Arm) --- .../bindings/dma/nvidia,tegra210-adma.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yam= l b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 =20 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 =20 - if: properties: --=20 2.34.1