From nobody Wed Oct 1 22:38:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B57E1269D17; Mon, 29 Sep 2025 12:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759148052; cv=pass; b=YRftDJpdtDj3RQU4c8ZY+LCtaoyajlpJGOeh+PtiihFuFYqLS8w5x54xWama0bu64XuuK5lQYrCtQiJ+sP3/utyirselvB2Zp9b6cvKlojOqLY895o68FLvTYx5TNOi5A8V2/h9BXUt5d2fNKB/0Z9wCua1kuFj1lQPTMRW7JK8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759148052; c=relaxed/simple; bh=1xshg8Db+FHyhdQQB7hIBQxxqN58HazFbh//LmsFlvc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f0cAqL7+qZV+dlRJOBUIrZTW+GyXEwMIh6nJKwasj0KAPRwwXgI0y2DKOGgLL7SVxXEQR2pao2P8gpzulVShuGFi2YQ0Wtg8+C5zwOn1nzaWeSN1uVoyshO3fVp8anTlzaS6mFoSF6QYBG/auXMpM7/AJp6asVX68eecTekwb4U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=IMTp+LqD; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="IMTp+LqD" ARC-Seal: i=1; a=rsa-sha256; t=1759148029; cv=none; d=zohomail.com; s=zohoarc; b=OvZXlL6457jQwi9TxNd45IkxRWD2OerRZgb3MCUSDRnMSfezAPvQErxldYHDckncC5kYhMr1xYsnvElxkMamr2SjL1dWnBo4LpVo84Yrci5cjyM5ru3kylhTg0/yjy/UhqiDS9+6laLwaFE/HvKX2UknjvNCyBr2i/Vv0rwoVWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759148029; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Po+W4jLTNNRztJahEXbzKFJ1FSG77lyfODqSfi5rmPk=; b=KBtolMeJM1giSs9rqZ6l1559ZViXOYEygMaNyACtn2BfWNfcdjeKXZalWiIlfM1yGn9EjdA7PTdA5R/S0Ui/T2/kMXFbUsuTDMluZjnw8E2QvsodRC+OaDDiDcNtA4KoSeBkiyqZ6HF/LjCmmjxzaRRke0qOF2bOKVxqTaNVCD8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1759148028; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Po+W4jLTNNRztJahEXbzKFJ1FSG77lyfODqSfi5rmPk=; b=IMTp+LqDmhl7qx7VaGEbd0T5h3HTBwBfZppj5Q4S532hGnSfMLJMQub1LZUfDVpS 4Tl1LgiOexwsTJMoLgqiBUfBEo95oQGjLXbo91YeWI3gqthxN3pdjG4m1i//N9E5pp6 FaBzpTBI5JCLGKDK3SKRK5HWhGfukTCgZ9phSWEM= Received: by mx.zohomail.com with SMTPS id 1759148027547606.8319661506675; Mon, 29 Sep 2025 05:13:47 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 29 Sep 2025 14:13:20 +0200 Subject: [PATCH 1/4] dt-bindings: clock: mediatek: Add clocks for MT8196 mfgpll Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250929-mtk-pll-rpm-v1-1-49541777878d@collabora.com> References: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> In-Reply-To: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Guangjie Song , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Yassine Oudjana Cc: kernel@collabora.com, Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The clock controllers for mfgpll, mfgpll-sc0, and mfgpll-sc1 all need CLK_TOP_MFG_EB to be on if their clock control registers are touched in any way. This was not known at the time this binding was written, as this dependency only came to light when I started poking at the MFlexGraphics hardware, where this undocumented peculiarity made itself known through SErrors being thrown during register reads. Add a clocks property to the binding to describe this relationship, and mark it as required for the affected clocks. Fixes: dd240e95f1be ("dt-bindings: clock: mediatek: Describe MT8196 clock c= ontrollers") Signed-off-by: Nicolas Frattaroli --- .../bindings/clock/mediatek,mt8196-sys-clock.yaml | 28 ++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-cl= ock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-cloc= k.yaml index 660ab64f390d2e722b7d3e25cf057926da318bc0..41aacd8d5f69050eebdf8392f7b= 652427632f491 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml @@ -45,6 +45,9 @@ properties: reg: maxItems: 1 =20 + clocks: + maxItems: 1 + '#clock-cells': const: 1 =20 @@ -90,6 +93,23 @@ required: =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-mfgpll-pll-ctrl + - mediatek,mt8196-mfgpll-sc0-pll-ctrl + - mediatek,mt8196-mfgpll-sc1-pll-ctrl + then: + properties: + clocks: + items: + - description: mfg_eb clock + required: + - clocks + examples: - | apmixedsys_clk: syscon@10000800 { @@ -104,4 +124,12 @@ examples: mediatek,hardware-voter =3D <&scp_hwv>; #clock-cells =3D <1>; }; + - | + #include =20 + clock-controller@4b810000 { + compatible =3D "mediatek,mt8196-mfgpll-pll-ctrl", "syscon"; + reg =3D <0x4b810000 0x400>; + clocks =3D <&topckgen CLK_TOP_MFG_EB>; + #clock-cells =3D <1>; + }; --=20 2.51.0 From nobody Wed Oct 1 22:38:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D60B30596F; Mon, 29 Sep 2025 12:14:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759148056; cv=pass; b=k+/XsbMHuw61l1VUc089OxKWwWSQCras1kdtq/+pwgMqLuqEWGtfkEwJYEC6SasZY4QoDUI3WZuZrsA5P2Bt5X3ZnzL0W9nrY5PgbqILSj0ajpwigZjUa7YCcZ/JrsqLL0PU6oZtmQWkrzq3Fw1sTILf077cs61oOxZHklXumXw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=nj+maPM7kXas+OqM/T0w/dYAI+0ixkQ2MCVze+Y7ZzA=; b=RCE5iGfBR82yrvR5TUn3Wqel6QJxsHUZ17XRU4CGBM7liyHiDlAFeiKOaqTRzkVC vlSuJfIPnDUXwAY4h1wjSp964L7b3PwL/0ONvp1vh72dA15zL1ZEI86a/HH4nwNjYrL UxVn/giYSGlxWE23kbtZa1SRHgOe6hDnsPmrAJrc= Received: by mx.zohomail.com with SMTPS id 1759148031644827.9697327445571; Mon, 29 Sep 2025 05:13:51 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 29 Sep 2025 14:13:21 +0200 Subject: [PATCH 2/4] clk: mediatek: Refactor pll registration to pass device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250929-mtk-pll-rpm-v1-2-49541777878d@collabora.com> References: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> In-Reply-To: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Guangjie Song , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Yassine Oudjana Cc: kernel@collabora.com, Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stands, mtk_clk_register_plls takes a struct device_node pointer as its first argument. This is a tragic happenstance, as it's trivial to get the device_node from a struct device, but the opposite not so much. The struct device is a much more useful thing to have passed down. Refactor mtk_clk_register_plls to take a struct device pointer instead of a struct device_node pointer, and fix up all users of this function. This will allow us to extend clk-pll with runtime PM things later. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701.c | 2 +- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++-- drivers/clk/mediatek/clk-mt6765.c | 2 +- drivers/clk/mediatek/clk-mt6779.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt7629.c | 2 +- drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++- drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +- drivers/clk/mediatek/clk-mt8196-mfg.c | 2 +- drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +- drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-pll.c | 7 ++++--- drivers/clk/mediatek/clk-pll.h | 6 +++--- 24 files changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 1e88ad8b93f4485ad40f842e19c68117e00a2fbe..d9f40fda73d1abc56ebc97ab755= bb48bd5f0991f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), + mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_div= s), clk_data); diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index a60622d251ff30fe8db2e596d87986a88f854e61..54b18e9f83f8f403460c77d8f5d= 4ea0737316774 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -119,7 +119,7 @@ static int clk_mt2712_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6735-apmixedsys.c index e0949911e8f7da7894b204012caefd0404cf8308..9e30c089a2092472bab889ede41= 9c41890c307a0 100644 --- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c @@ -93,8 +93,8 @@ static int clk_mt6735_apmixed_probe(struct platform_devic= e *pdev) return -ENOMEM; platform_set_drvdata(pdev, clk_data); =20 - ret =3D mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls, - ARRAY_SIZE(apmixedsys_plls), clk_data); + ret =3D mtk_clk_register_plls(&pdev->dev, apmixedsys_plls, + ARRAY_SIZE(apmixedsys_plls), clk_data); if (ret) { dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret); return ret; diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index d53731e7933f46d88ff180e43eb7163e52fb5b1c..60f6f9fa7dcf279631d0fa2eb30= a3bcbadef3225 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -740,7 +740,7 @@ static int clk_mt6765_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 86732f5acf93407a5aa99bc2f386f0728a06bb9b..4b9dcb910b03f1078212dc7089d= 7171d05de7e7f 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1220,7 +1220,7 @@ static int clk_mt6779_apmixed_probe(struct platform_d= evice *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index fb59e71af58e32d9419e036e3dbd28cdaa61cac3..ebf850ac57f540f2317e63dfabe= 94a953db3ae29 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -655,7 +655,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index 2350592d9a934f3ec8efb0cd8197e4c4fee49697..8a29eaab0cfcb7a389e09f8869b= 572d5886e2eaf 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -96,7 +96,7 @@ static int clk_mt7622_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index baf94e7bea373c59cb6333fdb483d00240b744c7..e154771b1b8bba7378af8a797c8= 1d0784b626e3b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -634,7 +634,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediat= ek/clk-mt7981-apmixed.c index e8211eb4e09e1a645f7e50a1e5814d29030c1757..6606b54fb376983ec7d49b00c2c= 0d1690c734058 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -76,7 +76,7 @@ static int clk_mt7981_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index 93751abe6be89784a102a0e5ac629d363ab3baaf..1c79418d08a77acf25cee914fb6= 573ac1707163e 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -74,7 +74,7 @@ static int clk_mt7986_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediat= ek/clk-mt7988-apmixed.c index 63d33a78cb48805f71aa6a74f8ed6b83f3b4fe22..416a4b88d100bb47bdb07e4f72b= c13208c8707a7 100644 --- a/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -86,7 +86,7 @@ static int clk_mt7988_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c index bdadc35c64cbd8987061c4442b8ff2f5fe50cc32..19e4ee489ec3905e92674ed0813= a9f60f9c28209 100644 --- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -57,7 +57,8 @@ static int clk_mt8135_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), + clk_data); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index adf576786696e0962dfd5147dfc8897bfaa48054..fb6c21bbeef81a383b56c8fada1= 799e0680676e5 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -105,7 +105,7 @@ static int clk_mt8167_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c index 551adbfd7ac9309bbc4f9beefe4f26230514f062..6242d4f5376e79346b2219b0a35= cf0c5ad755e49 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -155,7 +155,7 @@ static int clk_mt8183_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8188-apmixedsys.c index 21d7a9a2ab1af64cca6962960418d44c81dc664a..a1de596bff9945ca938504391e3= e33a4987d3a63 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -106,7 +106,7 @@ static int clk_mt8188_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index 8b45a3fad02f18df30e4c2ce2ba5b6338eae321f..a2d98ed58e34866b3d68bd0f85b= de339c258d822 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -66,7 +66,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_de= vice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), c= lk_data); + r =3D mtk_clk_register_plls(&pdev->dev, apusys_plls, + ARRAY_SIZE(apusys_plls), clk_data); if (r) goto free_apusys_pll_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8196-apmixedsys.c index 617f5449b88b8bcaf282e8ed8593b52413a233a8..c4ebb0170b82b979fbe7f03925f= 205325247d55d 100644 --- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c @@ -152,7 +152,8 @@ static int clk_mt8196_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks, + clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/c= lk-mt8196-mcu.c index 5cbcc411ae734c82b97bf099a645cb6aaa31d9c3..13642fc673c267a66027d1fa707= 3c9cfed68c682 100644 --- a/drivers/clk/mediatek/clk-mt8196-mcu.c +++ b/drivers/clk/mediatek/clk-mt8196-mcu.c @@ -122,7 +122,7 @@ static int clk_mt8196_mcu_probe(struct platform_device = *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, num_plls, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index ae1eb9de79ae2992b10a400c75e2e0324b100f66..8e09c0f7b7548f8e286671cea2d= ac64530b8ce47 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -105,7 +105,7 @@ static int clk_mt8196_mfg_probe(struct platform_device = *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, num_plls, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/media= tek/clk-mt8196-vlpckgen.c index d59a8a9d98550e897d18031d9bb814aa96d3cf57..7dcc164627c578ca93377425c3b= 21b46da4b4c28 100644 --- a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c +++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c @@ -664,7 +664,7 @@ static int clk_mt8196_vlp_probe(struct platform_device = *pdev) if (r) goto unregister_factors; =20 - r =3D mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls), + r =3D mtk_clk_register_plls(dev, vlp_plls, ARRAY_SIZE(vlp_plls), clk_data); if (r) goto unregister_muxes; diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c index f41b991a0178af3067b19a693512ec922af48e07..e331aa28a4bd58baf48a4aae160= 1cc80fc5661ac 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -133,7 +133,7 @@ static int clk_mt8365_apmixed_probe(struct platform_dev= ice *pdev) return PTR_ERR(hw); clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8516-apmixedsys.c index edd9174d2f2ff97a0c1198caa2a0b9c1ca40ffd2..2a6206cae2f087ff06fe60a6cf9= 6a0fa3143e567 100644 --- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -87,7 +87,7 @@ static int clk_mt8516_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index cd2b6ce551c6b0333cbe0a4f0d155ba2411f757a..5caf91ae9ddbe4f4d7052864adf= 0a5a70bda66bc 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include "clk-pll.h" @@ -404,7 +405,7 @@ void mtk_clk_unregister_pll(struct clk_hw *hw) kfree(pll); } =20 -int mtk_clk_register_plls(struct device_node *node, +int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data) { @@ -412,7 +413,7 @@ int mtk_clk_register_plls(struct device_node *node, int i; struct clk_hw *hw; =20 - base =3D of_iomap(node, 0); + base =3D of_iomap(dev->of_node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return -EINVAL; @@ -423,7 +424,7 @@ int mtk_clk_register_plls(struct device_node *node, =20 if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) { pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", - node, pll->id); + dev->of_node, pll->id); continue; } =20 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index d71c150ce83e4bb2fe78290c2d5570a90084246d..0e2b94b9cd4b56adceee3b04e9a= b24c2526471da 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -78,9 +78,9 @@ struct mtk_clk_pll { const struct mtk_pll_data *data; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=QxCZTFF4iG3STPzoFw46Bohn0VkTc+z5x9foKK+SKnc=; b=WQImkyqN0ts2FbkiuraOV8Q94f0LGL7NrIOMl3763L9oTAMp9z589bIxQ6vKTKhD 6C1BcSiyVxQlgw1kuU8jntB3wMprV2wmdwbPvvRXLA4M95f4YjfUJXZWHohXmPXFdX5 uJLBIS2geKleoqKyIJCfzOVfW2KPbCIDt2/t4T4A= Received: by mx.zohomail.com with SMTPS id 1759148035478164.29442178412774; Mon, 29 Sep 2025 05:13:55 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 29 Sep 2025 14:13:22 +0200 Subject: [PATCH 3/4] clk: mediatek: Pass device to clk_hw_register for PLLs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250929-mtk-pll-rpm-v1-3-49541777878d@collabora.com> References: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> In-Reply-To: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Guangjie Song , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Yassine Oudjana Cc: kernel@collabora.com, Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Passing the struct device pointer to clk_hw_register allows for runtime power management to work for the registered clocks. However, the mediatek PLL clocks do not do this. Change this by adding a struct device pointer argument to mtk_clk_register_pll, and fix up the only other user of it. Also add a new member to the struct mtk_clk_pll for the struct device pointer, which is set by mtk_clk_register_pll and is used by mtk_clk_register_pll_ops. If mtk_clk_register_pll is called with a NULL struct device pointer, then everything still works as expected; the clock core will simply treat them as previously, i.e. without runtime power management. Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-pll.c | 9 ++++++--- drivers/clk/mediatek/clk-pll.h | 4 +++- drivers/clk/mediatek/clk-pllfh.c | 2 +- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 5caf91ae9ddbe4f4d7052864adf0a5a70bda66bc..c4f9c06e5133dbc5902f261353c= 197fbde95e54d 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -366,7 +366,7 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, init.parent_names =3D &parent_name; init.num_parents =3D 1; =20 - ret =3D clk_hw_register(NULL, &pll->hw); + ret =3D clk_hw_register(pll->dev, &pll->hw); =20 if (ret) return ERR_PTR(ret); @@ -374,7 +374,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, return &pll->hw; } =20 -struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, +struct clk_hw *mtk_clk_register_pll(struct device *dev, + const struct mtk_pll_data *data, void __iomem *base) { struct mtk_clk_pll *pll; @@ -385,6 +386,8 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pl= l_data *data, if (!pll) return ERR_PTR(-ENOMEM); =20 + pll->dev =3D dev; + hw =3D mtk_clk_register_pll_ops(pll, data, base, pll_ops); if (IS_ERR(hw)) kfree(pll); @@ -428,7 +431,7 @@ int mtk_clk_register_plls(struct device *dev, continue; } =20 - hw =3D mtk_clk_register_pll(pll, base); + hw =3D mtk_clk_register_pll(dev, pll, base); =20 if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", pll->name, diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 0e2b94b9cd4b56adceee3b04e9ab24c2526471da..0f2a1d19eea78b7390b221af470= 16eb9897f3596 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -63,6 +63,7 @@ struct mtk_pll_data { */ =20 struct mtk_clk_pll { + struct device *dev; struct clk_hw hw; void __iomem *base_addr; void __iomem *pd_addr; @@ -110,7 +111,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, const struct mtk_pll_data *data, void __iomem *base, const struct clk_ops *pll_ops); -struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, +struct clk_hw *mtk_clk_register_pll(struct device *dev, + const struct mtk_pll_data *data, void __iomem *base); void mtk_clk_unregister_pll(struct clk_hw *hw); =20 diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index 83630ee07ee976bf980c8cf2dd35ea24c1b40821..62bfe4a480f14a0a742fb094aff= 0e6d1a79fe0c3 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -220,7 +220,7 @@ int mtk_clk_register_pllfhs(struct device_node *node, if (use_fhctl) hw =3D mtk_clk_register_pllfh(pll, pllfh, base); else - hw =3D mtk_clk_register_pll(pll, base); + hw =3D mtk_clk_register_pll(NULL, pll, base); =20 if (IS_ERR(hw)) { pr_err("Failed to register %s clk %s: %ld\n", --=20 2.51.0 From nobody Wed Oct 1 22:38:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E25AF3054F6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250929-mtk-pll-rpm-v1-4-49541777878d@collabora.com> References: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> In-Reply-To: <20250929-mtk-pll-rpm-v1-0-49541777878d@collabora.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Guangjie Song , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Yassine Oudjana Cc: kernel@collabora.com, Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The mfgpll clocks on mt8196 require that the MFG's EB clock is on if their control registers are touched in any way at all. Failing to ensure this results in a pleasant SError interrupt if the EB clock happens to be off. To achieve this, leverage the CCF core's runtime power management support. Define the necessary suspend/resume callbacks, add the necessary code to get RPM clocks from the DT, and make sure RPM is enabled before clock registration happens. For the RPM callbacks to really make much sense at all, we change the drvdata from clk_data to a new private struct, as is common in drivers across the Linux kernel. Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-mt8196-mfg.c | 104 +++++++++++++++++++++++++++---= ---- drivers/clk/mediatek/clk-pll.h | 2 + 2 files changed, 87 insertions(+), 19 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index 8e09c0f7b7548f8e286671cea2dac64530b8ce47..64cc0c037f62d7eab8d0e7fc00c= 05d122bf4130c 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "clk-mtk.h" #include "clk-pll.h" @@ -38,7 +39,7 @@ _flags, _rst_bar_mask, \ _pd_reg, _pd_shift, _tuner_reg, \ _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, _pcwbits) { \ + _pcw_reg, _pcw_shift, _pcwbits, _rpm_clks) { \ .id =3D _id, \ .name =3D _name, \ .reg =3D _reg, \ @@ -58,26 +59,60 @@ .pcw_shift =3D _pcw_shift, \ .pcwbits =3D _pcwbits, \ .pcwibits =3D MT8196_INTEGER_BITS, \ + .rpm_clk_names =3D _rpm_clks, \ + .num_rpm_clks =3D ARRAY_SIZE(_rpm_clks), \ } =20 +static const char * const mfgpll_rpm_clk_names[] =3D { + NULL +}; + static const struct mtk_pll_data mfg_ao_plls[] =3D { PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0, - BIT(0), MFGPLL_CON1, 24, 0, 0, 0, - MFGPLL_CON1, 0, 22), + BIT(0), MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22, + mfgpll_rpm_clk_names), }; =20 static const struct mtk_pll_data mfgsc0_ao_plls[] =3D { PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0, - MFGPLL_SC0_CON1, 0, 22), + MFGPLL_SC0_CON1, 0, 22, mfgpll_rpm_clk_names), }; =20 static const struct mtk_pll_data mfgsc1_ao_plls[] =3D { PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0, - MFGPLL_SC1_CON1, 0, 22), + MFGPLL_SC1_CON1, 0, 22, mfgpll_rpm_clk_names), }; =20 +struct clk_mt8196_mfg { + struct clk_hw_onecell_data *clk_data; + struct clk_bulk_data *rpm_clks; + unsigned int num_rpm_clks; +}; + +static int __maybe_unused clk_mt8196_mfg_resume(struct device *dev) +{ + struct clk_mt8196_mfg *clk_mfg =3D dev_get_drvdata(dev); + + if (!clk_mfg || !clk_mfg->rpm_clks) + return 0; + + return clk_bulk_prepare_enable(clk_mfg->num_rpm_clks, clk_mfg->rpm_clks); +} + +static int __maybe_unused clk_mt8196_mfg_suspend(struct device *dev) +{ + struct clk_mt8196_mfg *clk_mfg =3D dev_get_drvdata(dev); + + if (!clk_mfg || !clk_mfg->rpm_clks) + return 0; + + clk_bulk_disable_unprepare(clk_mfg->num_rpm_clks, clk_mfg->rpm_clks); + + return 0; +} + static const struct of_device_id of_match_clk_mt8196_mfg[] =3D { { .compatible =3D "mediatek,mt8196-mfgpll-pll-ctrl", .data =3D &mfg_ao_plls }, @@ -92,35 +127,60 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg); static int clk_mt8196_mfg_probe(struct platform_device *pdev) { const struct mtk_pll_data *plls; - struct clk_hw_onecell_data *clk_data; + struct clk_mt8196_mfg *clk_mfg; struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; const int num_plls =3D 1; - int r; + int r, i; =20 - plls =3D of_device_get_match_data(&pdev->dev); + plls =3D of_device_get_match_data(dev); if (!plls) return -EINVAL; =20 - clk_data =3D mtk_alloc_clk_data(num_plls); - if (!clk_data) + clk_mfg =3D devm_kzalloc(dev, sizeof(*clk_mfg), GFP_KERNEL); + if (!clk_mfg) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); + clk_mfg->num_rpm_clks =3D plls[0].num_rpm_clks; + + if (clk_mfg->num_rpm_clks) { + clk_mfg->rpm_clks =3D devm_kcalloc(dev, clk_mfg->num_rpm_clks, + sizeof(*clk_mfg->rpm_clks), + GFP_KERNEL); + if (!clk_mfg->rpm_clks) + return -ENOMEM; + + for (i =3D 0; i < clk_mfg->num_rpm_clks; i++) + clk_mfg->rpm_clks->id =3D plls[0].rpm_clk_names[i]; + + r =3D devm_clk_bulk_get(dev, clk_mfg->num_rpm_clks, + clk_mfg->rpm_clks); + if (r) + return r; + } + + clk_mfg->clk_data =3D mtk_alloc_clk_data(num_plls); + if (!clk_mfg->clk_data) + return -ENOMEM; + + dev_set_drvdata(dev, clk_mfg); + pm_runtime_enable(dev); + + r =3D mtk_clk_register_plls(dev, plls, num_plls, clk_mfg->clk_data); if (r) goto free_clk_data; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, + clk_mfg->clk_data); if (r) goto unregister_plls; =20 - platform_set_drvdata(pdev, clk_data); - return r; =20 unregister_plls: - mtk_clk_unregister_plls(plls, num_plls, clk_data); + mtk_clk_unregister_plls(plls, num_plls, clk_mfg->clk_data); free_clk_data: - mtk_free_clk_data(clk_data); + mtk_free_clk_data(clk_mfg->clk_data); =20 return r; } @@ -128,20 +188,26 @@ static int clk_mt8196_mfg_probe(struct platform_devic= e *pdev) static void clk_mt8196_mfg_remove(struct platform_device *pdev) { const struct mtk_pll_data *plls =3D of_device_get_match_data(&pdev->dev); - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + struct clk_mt8196_mfg *clk_mfg =3D dev_get_drvdata(&pdev->dev); struct device_node *node =3D pdev->dev.of_node; =20 of_clk_del_provider(node); - mtk_clk_unregister_plls(plls, 1, clk_data); - mtk_free_clk_data(clk_data); + mtk_clk_unregister_plls(plls, 1, clk_mfg->clk_data); + mtk_free_clk_data(clk_mfg->clk_data); } =20 +static DEFINE_RUNTIME_DEV_PM_OPS(clk_mt8196_mfg_pm_ops, + clk_mt8196_mfg_suspend, + clk_mt8196_mfg_resume, + NULL); + static struct platform_driver clk_mt8196_mfg_drv =3D { .probe =3D clk_mt8196_mfg_probe, .remove =3D clk_mt8196_mfg_remove, .driver =3D { .name =3D "clk-mt8196-mfg", .of_match_table =3D of_match_clk_mt8196_mfg, + .pm =3D pm_ptr(&clk_mt8196_mfg_pm_ops), }, }; module_platform_driver(clk_mt8196_mfg_drv); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 0f2a1d19eea78b7390b221af47016eb9897f3596..82b86b849a67359d8f23d828f50= 422081c2747e3 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -53,6 +53,8 @@ struct mtk_pll_data { u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ u8 pcw_chg_bit; u8 fenc_sta_bit; + const char * const *rpm_clk_names; + unsigned int num_rpm_clks; }; =20 /* --=20 2.51.0