From nobody Wed Oct 1 23:35:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94DB9216E23; Mon, 29 Sep 2025 07:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759132070; cv=pass; b=HLm0u4gufXKzlawT+xmb3xSyNy9FgfL6xbTj8PCTdmdXAedrOZpwMylBCpRIiF1bv5n1WWZdQyqNdUUvdrvEjcVmfVb1T87BRBcYvY088nYJD549uQ6avez6LhK1RDTyuiLn3r75hIQde2FsfDVEK/ktbgL1hLP+JAWDFsUBVlY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759132070; c=relaxed/simple; bh=B9+iSsDq6Y2Xn6HaaMA/DQYg/3MUR47dxKFt2/z8GUE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=neLo/Xb7RCvLbjZpdXn+Pwnlb8RGWAAtfcUeY0JNbz7oK92U63JMn0fVsp52c2ZmvpoHyC7H6ObnG7c0tI1j6uQ/EEP2AoTQHq55+7hqEyrospk4OGkI6aYAex//NUznUTPj91IMlPGXzWYr9+0+Vf51RT7Wy/OPNmt3LoGpHKo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=c0/GGHrp; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="c0/GGHrp" ARC-Seal: i=1; a=rsa-sha256; t=1759132047; cv=none; d=zohomail.com; s=zohoarc; b=XrA3wGSrk5E5/3gwXbRmmLyS2j4up4PPwPAuj4ZQrzPPhKnbDt5D2wqY0t0p2afvjkD2q06NFG2UalzPSd+ByhPJcdaWSyTQcAMP7ogpUY6AZ5k0fMPZ8JjpK3NPX72aIZLwQhEKnJUxKTirOsjJaEyRD24QiQLJwHPlJ11vHLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759132047; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=UJP0eLgRH0wRaLU3TMJnGjeyircwL3R7LtmsPmO+Txo=; b=BJJi++CSoGopb1HMVF87w9f+S7h0y+Dt88ViX0AFM14kXyDk4dgXd5QkM+/PB4gZayzWB0+YbumYYMTEjO4S+PqnjFYmRhMIrtvSWLewzvn/3HlA3EFo9Xw4l3kxs/1WX2vg+vjsELCnavz+EYgQGh6eCj+06WuLqTKjYcpLEy8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1759132046; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=UJP0eLgRH0wRaLU3TMJnGjeyircwL3R7LtmsPmO+Txo=; b=c0/GGHrpltjJlVrLtPSds4b4HVRFlOCpnDJ/5ZobxZrrWsZRvKeewzgloVJSvwFo +QneZ1d+1N7zOeQuBbVDJQxcvMlRStNMZyMYmeuBlQAJia6uaR0ADVUEousC/+Yg/Mj osdZHongSG3SDID6QemhsjPLVoHXUTFjtUaSU0N0= Received: by mx.zohomail.com with SMTPS id 1759132044551607.6876139326214; Mon, 29 Sep 2025 00:47:24 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 29 Sep 2025 09:46:45 +0200 Subject: [PATCH v5 2/7] dt-bindings: power: Add MT8196 GPU frequency control binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250929-mt8196-gpufreq-v5-2-3056e5ecf765@collabora.com> References: <20250929-mt8196-gpufreq-v5-0-3056e5ecf765@collabora.com> In-Reply-To: <20250929-mt8196-gpufreq-v5-0-3056e5ecf765@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled by some integration logic, referred to as "MFlexGraphics" by MediaTek, which comes in the form of an embedded controller running special-purpose firmware. This controller takes care of the regulators and PLL clock frequencies to squeeze the maximum amount of power out of the silicon. Add a binding which models it as a power domain. Signed-off-by: Nicolas Frattaroli --- .../bindings/power/mediatek,mt8196-gpufreq.yaml | 117 +++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufre= q.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..b9e43abaf8a42ce981ce16648fb= 3350b9c262015 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Power and Frequency Controller + +maintainers: + - Nicolas Frattaroli + +description: + A special-purpose embedded MCU to control power and frequency of GPU dev= ices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^power-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw-revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: core + - const: stack0 + - const: stack1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + memory-region: + items: + - description: phandle to the GPUEB shared memory + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - memory-region + - "#clock-cells" + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + power-controller@4b09fd00 { + compatible =3D "mediatek,mt8196-gpufreq"; + reg =3D <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names =3D "gpr", "rpc", "hw-revision"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names =3D "eb", "core", "stack0", "stack1"; + mboxes =3D <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names =3D "fast-dvfs-event", "gpufreq", "sleep", "timer", "fh= ctl", + "ccf", "fast-dvfs"; + memory-region =3D <&gpueb_shared_memory>; + #clock-cells =3D <1>; + #power-domain-cells =3D <0>; + }; --=20 2.51.0