From nobody Wed Dec 17 08:56:11 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7141029AB1D; Sun, 28 Sep 2025 06:40:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041620; cv=none; b=LmjZ0vgeTqosk4ijQqTpOmHN4efBRSrbMcxb+M4MRTXzq7e1rcf1MftrsODdrwm36YGtJQlJrA+0Q39RunLWNEX+4eJueawLqi/Tb7CLRNwzZcN6Lhg9YqHjyjC1BDS5/QU/iYNZdlJRBJwcM2ZEivBl8cVzaB6RAgFAVI1xmX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041620; c=relaxed/simple; bh=qsbwJQQL7BDBZsPlfUXxgitah970J+393ry2NZtZapg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mMpQcHA8qEaxxMFRFGHe9j790NDXLIgz9jjKb/Wc9qb9YNmd643HC6faLhaTM/vdcPLsfbwDQXVPsHEFftgnXK5LjQLBLpoSA8Agvyg2Nkvelz4hV8wFp/nyeLQG2R3cRiR/ESBRqGLSDNDBV/7IcMn+pODfpREMSFiHshWMxgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XKkk89gD; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XKkk89gD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759041619; x=1790577619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qsbwJQQL7BDBZsPlfUXxgitah970J+393ry2NZtZapg=; b=XKkk89gDguWO6rxGSEABKKLPmJX+5ZW865WCCz6zqPA/W+eElh24oV3T JxBsZWrEtQRm3rrId61DlLZecOz+Sbmh6ICoCZQCwfNNrv7UfPGQLmXmk uDeexY0D3BJ9SJl1qRxWQkxZVoaDp8EwpIX1MiRtkuL7EuS+afiBgIL94 7uv7Ugx9GsBbN+CyI7gLGzAllwJor5CdFLphhuwaeQJ48LS2nFjDZdW5z pw4JiRwYZe/mICLlDHvD0m2skP5vFSalnsn1/rfbLidUCulCEqpXfIutT xf8+uLCgoEqG1GFMxuWfbufp68oTtsjlyW25tsbj7glFed9A5gOg0ctHE A==; X-CSE-ConnectionGUID: fZ/4rpKsR327BCPyhD5Y5Q== X-CSE-MsgGUID: Hay836/rS827KbdkvRwrxg== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="61228531" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="61228531" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2025 23:40:18 -0700 X-CSE-ConnectionGUID: JkkdvK2bRP6cnrkTikKkXg== X-CSE-MsgGUID: 9vMjIjxQSc2Cp7nMKHeR8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,299,1751266800"; d="scan'208";a="177088848" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165]) by orviesa006.jf.intel.com with ESMTP; 27 Sep 2025 23:40:15 -0700 From: Xu Yilun To: linux-coco@lists.linux.dev, linux-pci@vger.kernel.org, dan.j.williams@intel.com Cc: yilun.xu@intel.com, yilun.xu@linux.intel.com, baolu.lu@linux.intel.com, zhenzhong.duan@intel.com, aneesh.kumar@kernel.org, bhelgaas@google.com, aik@amd.com, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] PCI/IDE: Add/export mini helpers for platform TSM drivers Date: Sun, 28 Sep 2025 14:27:54 +0800 Message-Id: <20250928062756.2188329-2-yilun.xu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250928062756.2188329-1-yilun.xu@linux.intel.com> References: <20250928062756.2188329-1-yilun.xu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These mini helpers are mainly for platform TSM drivers to setup root port side configuration. Root port side IDE settings may require platform specific firmware calls (e.g. TDX Connect [1]) so could not use pci_ide_stream_setup(), but may still share these mini helpers cause they also refer to definitions in IDE specification. [1]: https://lore.kernel.org/linux-coco/20250919142237.418648-28-dan.j.will= iams@intel.com/ Signed-off-by: Xu Yilun --- include/linux/pci-ide.h | 6 ++++++ drivers/pci/ide.c | 8 +++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h index a30f9460b04a..5adbd8b81f65 100644 --- a/include/linux/pci-ide.h +++ b/include/linux/pci-ide.h @@ -6,6 +6,11 @@ #ifndef __PCI_IDE_H__ #define __PCI_IDE_H__ =20 +#define PREP_PCI_IDE_SEL_RID_2(base, domain) \ + (FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | \ + FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, (base)) | \ + FIELD_PREP(PCI_IDE_SEL_RID_2_SEG, (domain))) + enum pci_ide_partner_select { PCI_IDE_EP, PCI_IDE_RP, @@ -61,6 +66,7 @@ struct pci_ide { struct tsm_dev *tsm_dev; }; =20 +int pci_ide_domain(struct pci_dev *pdev); struct pci_ide_partner *pci_ide_to_settings(struct pci_dev *pdev, struct p= ci_ide *ide); struct pci_ide *pci_ide_stream_alloc(struct pci_dev *pdev); void pci_ide_stream_free(struct pci_ide *ide); diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c index 10603f2d2319..7633b8e52399 100644 --- a/drivers/pci/ide.c +++ b/drivers/pci/ide.c @@ -345,12 +345,13 @@ void pci_ide_stream_unregister(struct pci_ide *ide) } EXPORT_SYMBOL_GPL(pci_ide_stream_unregister); =20 -static int pci_ide_domain(struct pci_dev *pdev) +int pci_ide_domain(struct pci_dev *pdev) { if (pdev->fm_enabled) return pci_domain_nr(pdev->bus); return 0; } +EXPORT_SYMBOL_GPL(pci_ide_domain); =20 struct pci_ide_partner *pci_ide_to_settings(struct pci_dev *pdev, struct p= ci_ide *ide) { @@ -420,10 +421,7 @@ void pci_ide_stream_setup(struct pci_dev *pdev, struct= pci_ide *ide) val =3D FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT, settings->rid_end); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val); =20 - val =3D FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | - FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, settings->rid_start) | - FIELD_PREP(PCI_IDE_SEL_RID_2_SEG, pci_ide_domain(pdev)); - + val =3D PREP_PCI_IDE_SEL_RID_2(settings->rid_start, pci_ide_domain(pdev)); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val); =20 /* --=20 2.25.1 From nobody Wed Dec 17 08:56:11 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C511729E0E9; Sun, 28 Sep 2025 06:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041623; cv=none; b=SB5LGWFJK+ow5zVcXjrvamCKngmzuRXzposGM0YsvRl49vs3GJwySrvEhHrvpN2WvKYtu6y2gPEl2DYeHySCgQF2VMnw8HcJIcB+6dQ2OLmgYmGeNNsUE/62SvuScqsU7ZVhlXdcNtJ+MZBJEksLuj9TCuHuFxQlHloU5vhAxfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041623; c=relaxed/simple; bh=pmRQYXRFavFbaxJ1kuJyWctAEkqk1UknTcndKobzj6w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RFrbc2Aab0LMxvUXT0MOpKdIYAkyTDskIjQPyQWLcBvSEv6I3NseWhRdzrRP5MVefnsNYoM3Vn8jpIUwQkj5P5neszD2bBqEa77mGMXZGQOv+NoFgwqnDccZpJ5tpnTd5emYHkxxV04bGGS2eiFKWcPA6RFTtJm/TmJ7u4P6Pfs= ARC-Authentication-Results: i=1; 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X-CSE-ConnectionGUID: 7g/h1uoYSQiBfLLixBOj4g== X-CSE-MsgGUID: k24F+BsEQ9m/V3TwUQN27g== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="61228536" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="61228536" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2025 23:40:21 -0700 X-CSE-ConnectionGUID: WQgZAgt5Rcu9J3I97SznOA== X-CSE-MsgGUID: NMDWgshiTrCVEMaktBWPqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,299,1751266800"; d="scan'208";a="177088872" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165]) by orviesa006.jf.intel.com with ESMTP; 27 Sep 2025 23:40:18 -0700 From: Xu Yilun To: linux-coco@lists.linux.dev, linux-pci@vger.kernel.org, dan.j.williams@intel.com Cc: yilun.xu@intel.com, yilun.xu@linux.intel.com, baolu.lu@linux.intel.com, zhenzhong.duan@intel.com, aneesh.kumar@kernel.org, bhelgaas@google.com, aik@amd.com, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] PCI/IDE: Add Address Association Register setup for RP Date: Sun, 28 Sep 2025 14:27:55 +0800 Message-Id: <20250928062756.2188329-3-yilun.xu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250928062756.2188329-1-yilun.xu@linux.intel.com> References: <20250928062756.2188329-1-yilun.xu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Address Association Register setup for Root Ports. The address ranges for RP side Address Association Registers should cover memory addresses for all PFs/VFs/downstream devices of the DSM device. A simple solution is to get the aggregated 32-bit and 64-bit address ranges from directly connected downstream port (either an RP or a switch port) and set into 2 Address Association Register blocks. There is a case the platform doesn't require Address Association Registers setup and provides no register block for RP (AMD). Will skip the setup in pci_ide_stream_setup(). Also imaging another case where there is only one block for RP. Prioritize 64-bit address ranges setup for it. No strong reason for the preference until a real use case comes. The Address Association Register setup for Endpoint Side is still uncertain so isn't supported in this patch. Take the oppotunity to export some mini helpers for Address Association Registers setup. TDX Connect needs the provided aggregated address ranges but will use specific firmware calls for actual setup instead of pci_ide_stream_setup(). Co-developed-by: Aneesh Kumar K.V Signed-off-by: Aneesh Kumar K.V Co-developed-by: Arto Merilainen Signed-off-by: Arto Merilainen Signed-off-by: Xu Yilun --- include/linux/pci-ide.h | 11 +++++++ drivers/pci/ide.c | 64 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 74 insertions(+), 1 deletion(-) diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h index 5adbd8b81f65..ac84fb611963 100644 --- a/include/linux/pci-ide.h +++ b/include/linux/pci-ide.h @@ -6,6 +6,15 @@ #ifndef __PCI_IDE_H__ #define __PCI_IDE_H__ =20 +#define SEL_ADDR1_LOWER GENMASK(31, 20) +#define SEL_ADDR_UPPER GENMASK_ULL(63, 32) +#define PREP_PCI_IDE_SEL_ADDR1(base, limit) \ + (FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) | \ + FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW, \ + FIELD_GET(SEL_ADDR1_LOWER, (base))) | \ + FIELD_PREP(PCI_IDE_SEL_ADDR_1_LIMIT_LOW, \ + FIELD_GET(SEL_ADDR1_LOWER, (limit)))) + #define PREP_PCI_IDE_SEL_RID_2(base, domain) \ (FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | \ FIELD_PREP(PCI_IDE_SEL_RID_2_BASE, (base)) | \ @@ -42,6 +51,8 @@ struct pci_ide_partner { unsigned int default_stream:1; unsigned int setup:1; unsigned int enable:1; + struct range mem32; + struct range mem64; }; =20 /** diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c index 7633b8e52399..8db1163737e5 100644 --- a/drivers/pci/ide.c +++ b/drivers/pci/ide.c @@ -159,7 +159,11 @@ struct pci_ide *pci_ide_stream_alloc(struct pci_dev *p= dev) struct stream_index __stream[PCI_IDE_HB + 1]; struct pci_host_bridge *hb; struct pci_dev *rp; + struct pci_dev *br; int num_vf, rid_end; + struct range mem32 =3D {}, mem64 =3D {}; + struct pci_bus_region region; + struct resource *res; =20 if (!pci_is_pcie(pdev)) return NULL; @@ -206,6 +210,24 @@ struct pci_ide *pci_ide_stream_alloc(struct pci_dev *p= dev) else rid_end =3D pci_dev_id(pdev); =20 + br =3D pci_upstream_bridge(pdev); + if (!br) + return NULL; + + res =3D &br->resource[PCI_BRIDGE_MEM_WINDOW]; + if (res->flags & IORESOURCE_MEM) { + pcibios_resource_to_bus(br->bus, ®ion, res); + mem32.start =3D region.start; + mem32.end =3D region.end; + } + + res =3D &br->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; + if (res->flags & IORESOURCE_PREFETCH) { + pcibios_resource_to_bus(br->bus, ®ion, res); + mem64.start =3D region.start; + mem64.end =3D region.end; + } + *ide =3D (struct pci_ide) { .pdev =3D pdev, .partner =3D { @@ -218,6 +240,8 @@ struct pci_ide *pci_ide_stream_alloc(struct pci_dev *pd= ev) .rid_start =3D pci_dev_id(pdev), .rid_end =3D rid_end, .stream_index =3D no_free_ptr(rp_stream)->stream_index, + .mem32 =3D mem32, + .mem64 =3D mem64, }, }, .host_bridge_stream =3D no_free_ptr(hb_stream)->stream_index, @@ -397,6 +421,21 @@ static void set_ide_sel_ctl(struct pci_dev *pdev, stru= ct pci_ide *ide, pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val); } =20 +static void set_ide_sel_addr(struct pci_dev *pdev, int pos, int assoc_idx, + struct range *mem) +{ + u32 val; + + val =3D PREP_PCI_IDE_SEL_ADDR1(mem->start, mem->end); + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(assoc_idx), val); + + val =3D FIELD_GET(SEL_ADDR_UPPER, mem->end); + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(assoc_idx), val); + + val =3D FIELD_GET(SEL_ADDR_UPPER, mem->start); + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(assoc_idx), val); +} + /** * pci_ide_stream_setup() - program settings to Selective IDE Stream regis= ters * @pdev: PCIe device object for either a Root Port or Endpoint Partner Po= rt @@ -410,6 +449,7 @@ static void set_ide_sel_ctl(struct pci_dev *pdev, struc= t pci_ide *ide, void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) { struct pci_ide_partner *settings =3D pci_ide_to_settings(pdev, ide); + u8 assoc_idx =3D 0; int pos; u32 val; =20 @@ -424,6 +464,21 @@ void pci_ide_stream_setup(struct pci_dev *pdev, struct= pci_ide *ide) val =3D PREP_PCI_IDE_SEL_RID_2(settings->rid_start, pci_ide_domain(pdev)); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val); =20 + /* + * Feel free to change the default stratagy, Intel & AMD don't directly + * setup RP registers. + * + * 64 bit memory first, assuming it's more popular. + */ + if (assoc_idx < pdev->nr_ide_mem && settings->mem64.end !=3D 0) { + set_ide_sel_addr(pdev, pos, assoc_idx, &settings->mem64); + assoc_idx++; + } + + /* 64 bit memory in lower block and 32 bit in higher block, any risk? */ + if (assoc_idx < pdev->nr_ide_mem && settings->mem32.end !=3D 0) + set_ide_sel_addr(pdev, pos, assoc_idx, &settings->mem32); + /* * Setup control register early for devices that expect * stream_id is set during key programming. @@ -445,7 +500,7 @@ EXPORT_SYMBOL_GPL(pci_ide_stream_setup); void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide) { struct pci_ide_partner *settings =3D pci_ide_to_settings(pdev, ide); - int pos; + int pos, i; =20 if (!settings) return; @@ -453,6 +508,13 @@ void pci_ide_stream_teardown(struct pci_dev *pdev, str= uct pci_ide *ide) pos =3D sel_ide_offset(pdev, settings); =20 pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0); + + for (i =3D 0; i < pdev->nr_ide_mem; i++) { + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0); + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0); + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0); + } + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, 0); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, 0); settings->setup =3D 0; --=20 2.25.1 From nobody Wed Dec 17 08:56:11 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A6D229E115; Sun, 28 Sep 2025 06:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041626; cv=none; b=EvTIyhzIEpC84vpABVfFladpM9eDVBXVh8n4JvL86P+ztxKT+xSGGDSd/j2MKVKTuoIXX2tqsXSnNND5l6vjR1fULK9kW+D7Kam4RwGvOWy0iKerEH4Sq0LmPt90r+GZE08quHVJOLOePEOhwDEmioEfQnQUH0EmwU1/V6Xotn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759041626; c=relaxed/simple; bh=cDTxcb4B+ODUAizKTHRF3o2YDVPO24Wtl1sX30pmf1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sSe7K2lcqeY8yBv8cj9JRt0Lcv1CMij5zIAVwBaKCumbtQYgKYSgZ++nUgC6EcblcOzRiiTadS938QDkjH0npoe5VomBHgbSjILsEKFaNI6U2umvqPSpSCoLLDzzsx7c+qYtPPyK2dXwwVvuCVfjPD8V/+us1N7QxF0Pj6AN7+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TPTD7scr; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TPTD7scr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759041625; x=1790577625; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cDTxcb4B+ODUAizKTHRF3o2YDVPO24Wtl1sX30pmf1Q=; b=TPTD7scr1CnpetPMDZOV29mFBXRku93aWeeoN42UVwBG14y9t20xtYec hgkVqDQvcxFo4O1qaptzTBONZFKsLKIh4wM7P6SvzLsyx5pWYSeDr9iW/ tdd9sR7nF916MCcRl/WyTbj0XPBQ4SUAyY7pKeqsz+VPTQJf00awsj/7n vl468+R/ghY0MTxJSowtETu4snM5ksTONve1zqK15y3k6X6LAu23iDbd8 iCFYSX9Hnd3F67V85IkP/Lvaed0wUMrjZ+RKJ0wyuUYrd1cbbEQYR+X3I SfMijTEtLyOyS8AFWLeAqVxQHKpgyQk6Ea+lcE1OWZhJvwA8hm5jeHs/z A==; X-CSE-ConnectionGUID: 8SYQ1ekNR2SI325oCifSow== X-CSE-MsgGUID: ee/IpVXTTh+aeSySfj4cAw== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="61228546" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="61228546" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2025 23:40:24 -0700 X-CSE-ConnectionGUID: VDyHmiQCR06ImWbm1f2Vhg== X-CSE-MsgGUID: yfO1NG4ISXmJrNPikFM3iA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,299,1751266800"; d="scan'208";a="177088889" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165]) by orviesa006.jf.intel.com with ESMTP; 27 Sep 2025 23:40:22 -0700 From: Xu Yilun To: linux-coco@lists.linux.dev, linux-pci@vger.kernel.org, dan.j.williams@intel.com Cc: yilun.xu@intel.com, yilun.xu@linux.intel.com, baolu.lu@linux.intel.com, zhenzhong.duan@intel.com, aneesh.kumar@kernel.org, bhelgaas@google.com, aik@amd.com, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] coco/tdx-host: Illustrate IDE Address Association Register setup Date: Sun, 28 Sep 2025 14:27:56 +0800 Message-Id: <20250928062756.2188329-4-yilun.xu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250928062756.2188329-1-yilun.xu@linux.intel.com> References: <20250928062756.2188329-1-yilun.xu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Not for devsec-staging. Just illustrate, can't compile. Please wait for: [RFC PATCH v2 00/27] PCI/TSM: TDX Connect: SPDM Session and IDE Establish= ment Signed-off-by: Xu Yilun --- drivers/virt/coco/tdx-host/tdx-host.c | 33 ++++----------------------- 1 file changed, 4 insertions(+), 29 deletions(-) diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c index 5553c63b4083..58777225b51e 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -387,29 +387,6 @@ static void tdx_ide_stream_key_stop(struct tdx_link *t= link) =20 DEFINE_FREE(tdx_ide_stream_key_stop, struct tdx_link *, if (!IS_ERR_OR_NUL= L(_T)) tdx_ide_stream_key_stop(_T)) =20 -/* OPEN: Should we add general address range support in pci/ide.c ? */ -static void setup_addr_range(struct pci_dev *pdev, - resource_size_t *start, resource_size_t *end) -{ - struct device *dev; - u32 devid; - int i; - - add_pdev_to_addr_range(pdev, start, end); - - for (i =3D 0; i < pci_num_vf(pdev); i++) { - devid =3D PCI_DEVID(pci_iov_virtfn_bus(pdev, i), - pci_iov_virtfn_devfn(pdev, i)); - - dev =3D bus_find_device(&pci_bus_type, NULL, &devid, - match_pci_dev_by_devid); - if (dev) { - add_pdev_to_addr_range(to_pci_dev(dev), start, end); - put_device(dev); - } - } -} - static void sel_stream_block_setup(struct pci_dev *pdev, struct pci_ide *i= de, u64 *rid_assoc1, u64 *rid_assoc2, u64 *addr_assoc1, u64 *addr_assoc2, @@ -422,12 +399,10 @@ static void sel_stream_block_setup(struct pci_dev *pd= ev, struct pci_ide *ide, *rid_assoc1 =3D FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT, setting->rid_end); *rid_assoc2 =3D PREP_PCI_IDE_SEL_RID_2(setting->rid_start, pci_ide_domain= (pdev)); =20 - /* Only one address association register block */ - setup_addr_range(pdev, &start, &end); - - *addr_assoc1 =3D PREP_PCI_IDE_SEL_ADDR1(start, end); - *addr_assoc2 =3D FIELD_GET(SEL_ADDR_UPPER, end); - *addr_assoc3 =3D FIELD_GET(SEL_ADDR_UPPER, start); + /* TDX Module enforces only one address association register block */ + *addr_assoc1 =3D PREP_PCI_IDE_SEL_ADDR1(setting->mem64.start, setting->me= m64.end); + *addr_assoc2 =3D FIELD_GET(SEL_ADDR_UPPER, setting->mem64.end); + *addr_assoc3 =3D FIELD_GET(SEL_ADDR_UPPER, setting->mem64.start); } =20 #define STREAM_INFO_RP_DEVFN GENMASK_ULL(7, 0) --=20 2.25.1