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charset="utf-8" Going by the generic "fsl,lynx-28g" compatible string and expecting all SerDes instantiations on all SoCs to use it was a mistake. They all share the same register map, sure, but the number of protocol converters and lanes which are instantiated differs in a way that isn't detectable by the programming interface. Using a separate compatible string per SerDes instantiation is sufficient for any device driver to distinguish these features and/or any instance-specific quirk. It also reflects how the SoC reference manual provides different tables with protocol combinations for each SerDes. NXP clearly documents these as not identical, and refers to them as such (SerDes 1, 2, etc). The other sufficient approach for Lynx 28G would be to list in the device tree all protocols supported by each lane. That would be insufficient for the very similar Lynx 10G SerDes however, for which there exists a higher degree of variability in the PCCR register values that need to be written per protocol. This attempt can be seen in this unmerged patch set for Lynx 10G: https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@se= co.com/ but that approach is more drawn-out and more prone to errors, whereas this one is more succinct and obviously correct. One aspect which is different with the per-SoC compatible strings is that they have one PHY provider for each lane (and #phy-cells =3D <0> in lane sub-nodes), rather than "fsl,lynx-28g" which has a single PHY provider for all lanes (and #phy-cells =3D <1> in the top-level node). This is done to fulfill Josua Mayer's request: https://lore.kernel.org/lkml/02270f62-9334-400c-b7b9-7e6a44dbbfc9@solid-run= .com/ to have OF nodes for each lane, so that we can further apply schemas such as Documentation/devicetree/bindings/phy/transmit-amplitude.yaml individually. This is the easiest and most intuitive way to describe that. The above is not the only electrical tuning that needs to be done, but rather the only one currently standardized in a schema. TX equalization parameters are TBD, but we need to not limit ourselves to just what currently exists. Luckily, we can overlap the modern binding format over the legacy one and they can coexist without interfering. Old kernels use compatible =3D "fsl,lynx-28g" and the top-level PHY provider, whereas new kernels probe on e.g. compatible =3D "fsl,lx2160a-serdes1" and use the per-lane PHY providers. Overlaying modern on top of legacy is only necessary for SerDes 1 and 2. LX2160A SerDes #3 (a non-networking SerDes) is not yet present in any device trees in circulation, and will only have the device-specific compatible (even though it shares the Lynx 28G programming model, specifying the "fsl,lynx-28g" compatible string for it provides no benefit that I can see). Change the expected name of the top-level node to "serdes", and update the example too. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Signed-off-by: Vladimir Oltean --- v2->v3: - re-add "fsl,lynx-28g" as fallback compatible, and #phy-cells =3D <1> in top-level "serdes" node - drop useless description texts - fix text formatting - schema is more lax to allow overlaying old and new required properties v1->v2: - drop the usage of "fsl,lynx-28g" as a fallback compatible - mark "fsl,lynx-28g" as deprecated - implement Josua's request for per-lane OF nodes for the new compatible strings .../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +++++++++++++++++- 1 file changed, 152 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Docu= mentation/devicetree/bindings/phy/fsl,lynx-28g.yaml index ff9f9ca0f19c..e8b3a48b9515 100644 --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml @@ -9,21 +9,123 @@ title: Freescale Lynx 28G SerDes PHY maintainers: - Ioana Ciornei =20 +description: + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Etherne= t) + present in multiple instances on NXP LX2160A and LX2162A SoCs. All insta= nces + share a common register map and programming model, however they differ in + supported protocols per lane in a way that is not detectable by said + programming model without prior knowledge. The distinction is made throu= gh + the compatible string. + properties: compatible: - enum: - - fsl,lynx-28g + oneOf: + - const: fsl,lynx-28g + deprecated: true + description: + Legacy compatibility string for Lynx 28G SerDes. Any assumption + regarding whether a certain lane supports a certain protocol may + be incorrect. Deprecated except when used as a fallback. Use + device-specific strings instead. + - items: + - const: fsl,lx2160a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2160a-serdes2 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes2 + - const: fsl,lynx-28g + - const: fsl,lx2160a-serdes3 =20 reg: maxItems: 1 =20 - "#phy-cells": - const: 1 + "#address-cells": true + + "#size-cells": true + + "#phy-cells": true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: Individual SerDes lane acting as PHY provider + + properties: + reg: + description: Lane index as seen in register map + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false =20 required: - compatible - reg - - "#phy-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,lynx-28g + then: + # Legacy case: parent is the PHY provider, cell encodes lane index + properties: + "#phy-cells": + const: 1 + required: + - "#phy-cells" + + - if: + properties: + compatible: + contains: + enum: + - fsl,lx2160a-serdes1 + - fsl,lx2160a-serdes2 + - fsl,lx2160a-serdes3 + - fsl,lx2162a-serdes1 + - fsl,lx2162a-serdes2 + then: + # Modern binding: lanes must have their own nodes + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + required: + - "#address-cells" + - "#size-cells" + + # LX2162A SerDes 1 has fewer lanes than the others + - if: + properties: + compatible: + contains: + const: fsl,lx2162a-serdes1 + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + enum: [4, 5, 6, 7] + else: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + enum: [0, 1, 2, 3, 4, 5, 6, 7] =20 additionalProperties: false =20 @@ -32,9 +134,52 @@ examples: soc { #address-cells =3D <2>; #size-cells =3D <2>; - serdes_1: phy@1ea0000 { - compatible =3D "fsl,lynx-28g"; + + serdes_1: serdes@1ea0000 { + compatible =3D "fsl,lx2160a-serdes1", "fsl,lynx-28g"; reg =3D <0x0 0x1ea0000 0x0 0x1e30>; + #address-cells =3D <1>; + #size-cells =3D <0>; #phy-cells =3D <1>; + + phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + }; + + phy@1 { + reg =3D <1>; + #phy-cells =3D <0>; + }; + + phy@2 { + reg =3D <2>; + #phy-cells =3D <0>; + }; + + phy@3 { + reg =3D <3>; + #phy-cells =3D <0>; + }; + + phy@4 { + reg =3D <4>; + #phy-cells =3D <0>; + }; + + phy@5 { + reg =3D <5>; + #phy-cells =3D <0>; + }; + + phy@6 { + reg =3D <6>; + #phy-cells =3D <0>; + }; + + phy@7 { + reg =3D <7>; + #phy-cells =3D <0>; + }; }; }; --=20 2.34.1