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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL02EPF0001A103.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.9 via Frontend Transport; Fri, 26 Sep 2025 10:54:26 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 26 Sep 2025 03:54:25 -0700 Received: from xhdradheys41.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 26 Sep 2025 03:54:19 -0700 From: Manikanta Guntupalli To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , Manikanta Guntupalli Subject: [PATCH V8 3/5] i3c: fix big-endian FIFO transfers Date: Fri, 26 Sep 2025 16:23:47 +0530 Message-ID: <20250926105349.2932952-4-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250926105349.2932952-1-manikanta.guntupalli@amd.com> References: <20250926105349.2932952-1-manikanta.guntupalli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|BY5PR12MB4116:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ac641e1-bc5a-4c7e-b576-08ddfceb0fba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024|921020|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2025 10:54:26.7450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ac641e1-bc5a-4c7e-b576-08ddfceb0fba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4116 Content-Type: text/plain; charset="utf-8" From: Arnd Bergmann Short MMIO transfers that are not a multiple of four bytes in size need a special case for the final bytes, however the existing implementation is not endian-safe and introduces an incorrect byteswap on big-endian kernels. This usually does not cause problems because most systems are little-endian and most transfers are multiple of four bytes long, but still needs to be fixed to avoid the extra byteswap. Change the special case for both i3c_writel_fifo() and i3c_readl_fifo() to use non-byteswapping writesl() and readsl() with a single element instead of the byteswapping writel()/readl() that are meant for individual MMIO registers. As data is copied between a FIFO and a memory buffer, the writesl()/readsl() loops are typically based on __raw_readl()/ __raw_writel(), resulting in the order of bytes in the FIFO to match the order in the buffer, regardless of the CPU endianess. The earlier versions in the dw-i3c and i3c-master-cdns had a correct implementation, but the generic version that was recently added broke it. Fixes: 733b439375b4 ("i3c: master: Add inline i3c_readl_fifo() and i3c_writ= el_fifo()") Cc: Manikanta Guntupalli Signed-off-by: Arnd Bergmann Reviewed-by: Jorge Marques Signed-off-by: Manikanta Guntupalli --- Changes since V8: This patch has been included in this series as the current series depends o= n it. https://patchwork.kernel.org/project/linux-i3c/patch/20250924201837.3691486= -1-arnd@kernel.org/ --- drivers/i3c/internals.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h index 0d857cc68cc5..77d56415cb99 100644 --- a/drivers/i3c/internals.h +++ b/drivers/i3c/internals.h @@ -38,7 +38,11 @@ static inline void i3c_writel_fifo(void __iomem *addr, c= onst void *buf, u32 tmp =3D 0; =20 memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); - writel(tmp, addr); + /* + * writesl() instead of writel() to keep FIFO byte orderer to match + * the order in the buffer regardless of the CPU endianess. + */ + writesl(addr, &tmp, 1); } } =20 @@ -55,7 +59,11 @@ static inline void i3c_readl_fifo(const void __iomem *ad= dr, void *buf, if (nbytes & 3) { u32 tmp; =20 - tmp =3D readl(addr); + /* + * readsl() instead of readl() to keep FIFO byte orderer to match + * the order in the buffer regardless of the CPU endianess. + */ + readsl(addr, &tmp, 1); memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3); } } --=20 2.34.1