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Fri, 26 Sep 2025 07:40:11 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org, m.szyprowski@samsung.com, jh80.chung@samsung.com, shradha.t@samsung.com Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sh86.bae@samsung.com Subject: [PATCH 1/4] dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920 Date: Fri, 26 Sep 2025 16:39:16 +0900 Message-ID: <20250926073921.1000866-2-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250926073921.1000866-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250926074011epcas2p438f7edb31c720c0950e9df986983f5a5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250926074011epcas2p438f7edb31c720c0950e9df986983f5a5 References: <20250926073921.1000866-1-sh86.bae@samsung.com> Add hsi0 compatible for ExynosAutov920 PCIe settings for: - PCIe PHY power control - PLL settings for PCIe - PCIe device direction (RC/EP) Signed-off-by: Sanghoon Bae --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index d27ed6c9d61e..a44fd24ed0ea 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -30,6 +30,7 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynosautov920-hsi0-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg --=20 2.45.2 From nobody Wed Oct 1 23:35:34 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96CD328934D for ; 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Fri, 26 Sep 2025 07:40:19 +0000 (GMT) Received: from epcas2p2.samsung.com (unknown [182.195.36.69]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4cY2YZ0hjmz6B9m9; Fri, 26 Sep 2025 07:40:18 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20250926074017epcas2p18fb2fc616b92dc04ad9e018151c2ba29~oxSUQRHA61723517235epcas2p1N; Fri, 26 Sep 2025 07:40:17 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250926074017epsmtip2605014d87cb2a679f123ac72d62d40f4~oxSULQqe31191711917epsmtip21; Fri, 26 Sep 2025 07:40:17 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org, m.szyprowski@samsung.com, jh80.chung@samsung.com, shradha.t@samsung.com Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sh86.bae@samsung.com Subject: [PATCH 2/4] dt-bindings: phy: Add PCIe PHY support for ExynosAutov920 SoC Date: Fri, 26 Sep 2025 16:39:17 +0900 Message-ID: <20250926073921.1000866-3-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250926073921.1000866-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250926074017epcas2p18fb2fc616b92dc04ad9e018151c2ba29 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250926074017epcas2p18fb2fc616b92dc04ad9e018151c2ba29 References: <20250926073921.1000866-1-sh86.bae@samsung.com> Since the Exynosautov920 SoC uses the Samsung PCIe PHY, add support for it in the Exynosautov920 PCIe PHY bindings. The Exynosautov920 SoC includes two PHY instances: one for a 4-lane PHY and another for a 2-lane PHY. Each PHY can be used by separate controllers through the bifurcation option. Therefore, from 2 up to 4 PCIe controllers can be supported and connected with this PHY driver. PCIe lane number is used to distinguish each PHY instance. This is required since two PHY instances on ExynosAutov920 is not identical. On PHY driver code, need to check each instance and different settings. Signed-off-by: Sanghoon Bae --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml index 6295472696db..1e8b88d2cd56 100644 --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -19,6 +19,7 @@ properties: - samsung,exynos5433-pcie-phy - tesla,fsd-pcie-phy0 - tesla,fsd-pcie-phy1 + - samsung,exynosautov920-pcie-phy =20 reg: minItems: 1 @@ -34,6 +35,10 @@ properties: description: phandle for FSYS sysreg interface, used to control sysreg registers bits for PCIe PHY =20 + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4] + allOf: - if: properties: @@ -42,6 +47,7 @@ allOf: enum: - tesla,fsd-pcie-phy0 - tesla,fsd-pcie-phy1 + - samsung,exynosautov920-pcie-phy then: properties: reg: @@ -52,6 +58,14 @@ allOf: properties: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-pcie-phy + then: + required: + - num-lanes =20 required: - "#phy-cells" --=20 2.45.2 From nobody Wed Oct 1 23:35:34 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C618928BAB1 for ; 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Fri, 26 Sep 2025 07:40:22 +0000 (GMT) Received: from epcas2p2.samsung.com (unknown [182.195.36.68]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4cY2Yd6GH7z2SSKg; Fri, 26 Sep 2025 07:40:21 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20250926074021epcas2p36a8dc02c84c9ca11e2318a1a8931d68a~oxSXvVrYl2057720577epcas2p3b; Fri, 26 Sep 2025 07:40:21 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250926074021epsmtip2d9a38292d8fdfabc0655d0e0ed648b74~oxSXmH4d41194111941epsmtip2r; Fri, 26 Sep 2025 07:40:21 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org, m.szyprowski@samsung.com, jh80.chung@samsung.com, shradha.t@samsung.com Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sh86.bae@samsung.com Subject: [PATCH 3/4] arm64: dts: ExynosAutov920: add PCIe PHY DT nodes Date: Fri, 26 Sep 2025 16:39:18 +0900 Message-ID: <20250926073921.1000866-4-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250926073921.1000866-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250926074021epcas2p36a8dc02c84c9ca11e2318a1a8931d68a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250926074021epcas2p36a8dc02c84c9ca11e2318a1a8931d68a References: <20250926073921.1000866-1-sh86.bae@samsung.com> Add pcie_4l_phy, pcie_2l_phy dt node for all PCIe PHY instances in ExynosAutov920 SoC. Add HSI sysreg to control PCIe sysreg registers. Signed-off-by: Sanghoon Bae --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 2cb8041c8a9f..9e45bfcd7980 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1021,12 +1021,40 @@ cmu_hsi0: clock-controller@16000000 { "noc"; }; =20 + syscon_hsi0: syscon@16030000 { + compatible =3D "samsung,exynosautov920-hsi0-sysreg", + "syscon"; + reg =3D <0x16030000 0x1000>; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible =3D "samsung,exynosautov920-pinctrl"; reg =3D <0x16040000 0x10000>; interrupts =3D ; }; =20 + pcie_2l_phy: pcie-phy2l@161c6000{ + compatible =3D "samsung,exynosautov920-pcie-phy"; + reg =3D <0x161c6000 0x2000>, + <0x161d0000 0xb000>; + #phy-cells =3D <0>; + samsung,pmu-syscon =3D <&pmu_system_controller>; + samsung,fsys-sysreg =3D <&syscon_hsi0>; + num-lanes =3D <2>; + status =3D "disabled"; + }; + + pcie_4l_phy: pcie-phy4l@163c6000{ + compatible =3D "samsung,exynosautov920-pcie-phy"; + reg =3D <0x163c6000 0x2000>, + <0x163d0000 0xb000>; + #phy-cells =3D <0>; + samsung,pmu-syscon =3D <&pmu_system_controller>; + samsung,fsys-sysreg =3D <&syscon_hsi0>; + num-lanes =3D <4>; + status =3D "disabled"; + }; + cmu_hsi1: clock-controller@16400000 { compatible =3D "samsung,exynosautov920-cmu-hsi1"; reg =3D <0x16400000 0x8000>; --=20 2.45.2 From nobody Wed Oct 1 23:35:34 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B11FB28934D for ; Fri, 26 Sep 2025 07:40:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758872429; cv=none; b=nj1TYVvTNHtwWA8MHucdcHsr231EAQpQ68Rct5Kqhx4vfbihdYSol0FUPqE1wbOdVLRMWYmw3xhXRRzhXdcAzjSJnPcezBSJZV4ep7fZ7mX1uShoHOiry1wTh0qKaxkl9070cXF2y2/DI4+Kdn//a4Gcwslrzeo4ZODtkIzKwx4= ARC-Message-Signature: i=1; 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Fri, 26 Sep 2025 07:40:22 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250926074022epsmtip2570a9e2d16c5857aa194b0b3c2963907~oxSYzvL2p1189511895epsmtip2W; Fri, 26 Sep 2025 07:40:22 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org, m.szyprowski@samsung.com, jh80.chung@samsung.com, shradha.t@samsung.com Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sh86.bae@samsung.com Subject: [PATCH 4/4] phy: exynos: Add PCIe PHY support for ExynosAutov920 SoC Date: Fri, 26 Sep 2025 16:39:19 +0900 Message-ID: <20250926073921.1000866-5-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250926073921.1000866-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250926074022epcas2p3aa1179b587beac076ef5942004c7d099 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250926074022epcas2p3aa1179b587beac076ef5942004c7d099 References: <20250926073921.1000866-1-sh86.bae@samsung.com> Add PCIe PHY support for ExynosAutov920 SoC Signed-off-by: Sanghoon Bae --- drivers/phy/samsung/phy-exynos-pcie.c | 231 ++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/ph= y-exynos-pcie.c index 5a55a22f9661..5b9d65f8f6c7 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -129,14 +129,87 @@ #define FSD_PCIE_SYSREG_PHY_1_CMN_RSTN BIT(1) #define FSD_PCIE_SYSREG_PHY_1_INIT_RSTN BIT(3) =20 +/* Exynosautov920 register offsets and bits */ +/* EA920: PHY registers */ +#define EA920_PCIE_PHY0_COMMON_CTRL 0x1000 +#define EA920_PCIE_PHY_RTUNE_REQ 0x10000001 +#define EA920_PCIE_PHY0_GEN_CTRL_1 0x1010 +#define EA920_PCIE_PHY0_REFA_CLK_SEL_MASK GENMASK(17, 16) +#define EA920_PCIE_PHY0_REFB_CLK_SEL_MASK GENMASK(19, 18) +#define EA920_PCIE_PHY0_PHY0_SRAM_BYPASS BIT(10) +#define EA920_PCIE_PHY0_PHY0_SRAM_EXT_LD_DONE BIT(11) +#define EA920_PCIE_PHY0_REFA_B_ALT1 0x061a0060 +#define EA920_PCIE_PHY0_REFA_B_ALT0 0x06100060 +#define EA920_PCIE_PHY0_REFA_B_PAD 0x06150060 +#define EA920_PCIE_PHY0_SRAM_INIT_DONE 31 +#define EA920_PCIE_PHY_EXT_TX_ROPLL_POSTDIV_CTRL 0x11a8 +#define EA920_PCIE_PHY_ROPLL_POSTDIV_VAL 0x1249 +#define EA920_PCIE_PHY_EXT_TX_OVRD_EN_CTRL 0x11c4 +#define EA920_PCIE_PHY_ROPLL_POSTDIV_OVRD_EN_VAL (0xf << 0) +#define EA920_PCIE_PIPE_LANEX_LANEPLL_BYPASS 0x1384 +#define EA920_PCIE_PIPE_BYPASS_MODE_CTRL_VAL1 0x0 +#define EA920_PCIE_PIPE_BYPASS_MODE_CTRL_VAL2 0x0 +/* EA920: SOC CTRL registers */ +#define EA920_PCIE_REFCLK_CTRL_SOC_OPTION_0 0xa200 +#define EA920_PCIE_REFCLK_OPTION0_RC 0x103f5 +#define EA920_PCIE_REFCLK_CTRL_SOC_OPTION_1 0xa204 +#define EA920_PCIE_REFCLK_OPTION1_RC 0x30c00 +/* EA920: PMU registers */ +#define EA920_PCIE_PHY_4L_CONFIGURATION 0x700 +#define EA920_PCIE_PHY_2L_CONFIGURATION 0x704 +#define EA920_PCIE_PHY_CFG_EN_PHY (0x1 << 0) +/* EA920: GEN SYS registers */ +#define EA920_GENERAL_SS_RST_CTRL_1 0x48 +#define EA920_GENERAL_RST_PE0_SOFT_WARM_PHY_RESET GENMASK(2, 1) +#define EA920_GENERAL_RST_PE1_SOFT_COLD_RESET (0x1 << 8) +#define EA920_GENERAL_RST_PE1_SOFT_WARM_PHY_RESET (0x3 << 9) +#define EA920_GENERAL_RST_PE0_SOFT_WARM_RESET (0x1 << 1) +#define EA920_GENERAL_RST_PE1_SOFT_WARM_RESET (0x1 << 9) +#define EA920_GENERAL_RST_PE0_1_PHY_EN 0x808 +#define EA920_PHY_TIMEOUT 2000 +/* EA920: SYSREG registers */ +#define EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_4L 0x670 +#define EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_2L 0x4 +#define EA920_HSI0_PCIE_PHY_TEST_PWRDWN_MSK BIT(0) +#define EA920_HSI0_PCIE_PHY_TEST_PWRDUP 0x0 +#define EA920_HSI0_PCIE_PHY_TEST_PWRDWN 0x1 +#define EA920_HSI0_PCIE_GEN5_4LA_PHY_CTRL 0x828 +#define EA920_HSI0_PCIE_GEN5_2LA_PHY_CTRL 0x868 +#define EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_MSK GENMASK(27, 24) +#define EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_RC_A 0x4 +#define EA920_HSI0_PLL_REG0 0x600 +#define EA920_HSI0_PLL_FOUTEN_MSK BIT(8) +#define EA920_HSI0_PLL_FOUTEN 0x1 +#define EA920_HSI0_PLL_REG1 0x604 +#define EA920_HSI0_PLL_FOUTPOSTDIVEN_MSK BIT(0) +#define EA920_HSI0_PLL_FOUTPOSTDIVEN 0x1 +#define EA920_HSI0_PLL_REG2 0x608 +#define EA920_HSI0_PLL_PLLEN_MSK BIT(24) +#define EA920_HSI0_PLL_PLLEN 0x1 +#define EA920_HSI0_CLKBUF0_REG0 0x620 +#define EA920_HSI0_CLKBUF1_REG0 0x630 +#define EA920_HSI0_CLKBUF2_REG0 0x640 +#define EA920_HSI0_CLKBUF3_REG0 0x650 +#define EA920_HSI0_CLKBUF_IMP_CTRL_MSK BIT(0) +#define EA920_HSI0_CLKBUF_IMP_CTRL 0x1 + /* For Exynos pcie phy */ struct exynos_pcie_phy { void __iomem *base; void __iomem *pcs_base; struct regmap *pmureg; struct regmap *fsysreg; + int num_lanes; }; =20 +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset) +{ + u32 data =3D 0; + + data =3D readl(base + offset); + return data; +} + static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) { writel(val, base + offset); @@ -398,6 +471,152 @@ static int fsd_pcie_phy1_init(struct phy *phy) return 0; } =20 +static int exynosautov920_pcie_phy_init(struct phy *phy) +{ + struct exynos_pcie_phy *ep =3D phy_get_drvdata(phy); + u32 val; + int timeout; + + /* PHY on */ + if (ep->num_lanes =3D=3D 4) { + regmap_update_bits(ep->pmureg, + EA920_PCIE_PHY_4L_CONFIGURATION, + BIT(0), EA920_PCIE_PHY_CFG_EN_PHY); + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_4L, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN_MSK, + EA920_HSI0_PCIE_PHY_TEST_PWRDUP); + + /* SYSREG set to RC */ + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_4LA_PHY_CTRL, + EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_MSK, + EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_RC_A); + } else if (ep->num_lanes =3D=3D 2) { + /* In 2L phy, 4L phy pmu should isolation off first */ + regmap_update_bits(ep->pmureg, + EA920_PCIE_PHY_4L_CONFIGURATION, + BIT(0), EA920_PCIE_PHY_CFG_EN_PHY); + regmap_update_bits(ep->pmureg, + EA920_PCIE_PHY_2L_CONFIGURATION, + BIT(0), EA920_PCIE_PHY_CFG_EN_PHY); + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_2L, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN_MSK, + EA920_HSI0_PCIE_PHY_TEST_PWRDUP); + /* SYSREG set to RC */ + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_2LA_PHY_CTRL, + EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_MSK, + EA920_HSI0_PCIE_IP_CTRL_DEV_TYPE_RC_A); + } + + /* SOC control */ + exynos_pcie_phy_writel(ep->pcs_base, EA920_PCIE_REFCLK_OPTION0_RC, + EA920_PCIE_REFCLK_CTRL_SOC_OPTION_0); + exynos_pcie_phy_writel(ep->pcs_base, EA920_PCIE_REFCLK_OPTION1_RC, + EA920_PCIE_REFCLK_CTRL_SOC_OPTION_1); + + /* PLL setting */ + regmap_update_bits(ep->fsysreg, EA920_HSI0_PLL_REG0, + EA920_HSI0_PLL_FOUTEN_MSK, EA920_HSI0_PLL_FOUTEN); + regmap_update_bits(ep->fsysreg, EA920_HSI0_PLL_REG1, + EA920_HSI0_PLL_FOUTPOSTDIVEN_MSK, + EA920_HSI0_PLL_FOUTPOSTDIVEN); + regmap_update_bits(ep->fsysreg, EA920_HSI0_PLL_REG2, + EA920_HSI0_PLL_PLLEN_MSK, EA920_HSI0_PLL_PLLEN); + regmap_update_bits(ep->fsysreg, EA920_HSI0_CLKBUF0_REG0, + EA920_HSI0_CLKBUF_IMP_CTRL_MSK, + EA920_HSI0_CLKBUF_IMP_CTRL); + regmap_update_bits(ep->fsysreg, EA920_HSI0_CLKBUF1_REG0, + EA920_HSI0_CLKBUF_IMP_CTRL_MSK, + EA920_HSI0_CLKBUF_IMP_CTRL); + regmap_update_bits(ep->fsysreg, EA920_HSI0_CLKBUF2_REG0, + EA920_HSI0_CLKBUF_IMP_CTRL_MSK, + EA920_HSI0_CLKBUF_IMP_CTRL); + regmap_update_bits(ep->fsysreg, EA920_HSI0_CLKBUF3_REG0, + EA920_HSI0_CLKBUF_IMP_CTRL_MSK, + EA920_HSI0_CLKBUF_IMP_CTRL); + + /* REFCLK setting */ + val =3D exynos_pcie_phy_readl(ep->base, EA920_PCIE_PHY0_GEN_CTRL_1); + exynos_pcie_phy_writel(ep->base, val & + ~EA920_PCIE_PHY0_REFA_CLK_SEL_MASK, + EA920_PCIE_PHY0_GEN_CTRL_1); + exynos_pcie_phy_writel(ep->base, + val & ~EA920_PCIE_PHY0_REFB_CLK_SEL_MASK, + EA920_PCIE_PHY0_GEN_CTRL_1); + /* wait for REF CLK source change */ + usleep_range(100, 110); + exynos_pcie_phy_writel(ep->base, EA920_PCIE_PHY_RTUNE_REQ, + EA920_PCIE_PHY0_COMMON_CTRL); + exynos_pcie_phy_writel(ep->base, EA920_PCIE_PHY_ROPLL_POSTDIV_VAL, + EA920_PCIE_PHY_EXT_TX_ROPLL_POSTDIV_CTRL); + exynos_pcie_phy_writel(ep->base, + EA920_PCIE_PHY_ROPLL_POSTDIV_OVRD_EN_VAL, + EA920_PCIE_PHY_EXT_TX_OVRD_EN_CTRL); + exynos_pcie_phy_writel(ep->base, EA920_PCIE_PIPE_BYPASS_MODE_CTRL_VAL1, + EA920_PCIE_PIPE_LANEX_LANEPLL_BYPASS); + exynos_pcie_phy_writel(ep->base, EA920_PCIE_PIPE_BYPASS_MODE_CTRL_VAL2, + EA920_PCIE_PIPE_LANEX_LANEPLL_BYPASS); + exynos_pcie_phy_writel(ep->base, EA920_PCIE_PHY0_REFA_B_ALT0, + EA920_PCIE_PHY0_GEN_CTRL_1); + + /* PHY warm reset */ + val =3D exynos_pcie_phy_readl(ep->base, EA920_GENERAL_SS_RST_CTRL_1); + exynos_pcie_phy_writel(ep->base, val | + EA920_GENERAL_RST_PE0_SOFT_WARM_PHY_RESET, + EA920_GENERAL_SS_RST_CTRL_1); + usleep_range(10, 12); + exynos_pcie_phy_writel(ep->base, val & + ~EA920_GENERAL_RST_PE0_SOFT_WARM_PHY_RESET, + EA920_GENERAL_SS_RST_CTRL_1); + + /* Set SRAM bypass */ + val =3D exynos_pcie_phy_readl(ep->base, EA920_PCIE_PHY0_GEN_CTRL_1); + exynos_pcie_phy_writel(ep->base, val | EA920_PCIE_PHY0_PHY0_SRAM_BYPASS, + EA920_PCIE_PHY0_GEN_CTRL_1); + + /* Wait SRAM init */ + timeout =3D 0; + do { + udelay(1); + timeout++; + if (timeout >=3D EA920_PHY_TIMEOUT) + return -ETIME; + } while (!(exynos_pcie_phy_readl(ep->base, + EA920_PCIE_PHY0_GEN_CTRL_1) >> + EA920_PCIE_PHY0_SRAM_INIT_DONE)); + + timeout =3D 0; + val =3D exynos_pcie_phy_readl(ep->base, EA920_PCIE_PHY0_GEN_CTRL_1); + exynos_pcie_phy_writel(ep->base, val | + EA920_PCIE_PHY0_PHY0_SRAM_EXT_LD_DONE, + EA920_PCIE_PHY0_GEN_CTRL_1); + /* wait for PHY init done */ + mdelay(100); + + return 0; +} + +static int exynosautov920_pcie_phy_exit(struct phy *phy) +{ + struct exynos_pcie_phy *ep =3D phy_get_drvdata(phy); + + if (ep->num_lanes =3D=3D 4) + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_4L, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN_MSK, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN); + else if (ep->num_lanes =3D=3D 2) + regmap_update_bits(ep->fsysreg, + EA920_HSI0_PCIE_GEN5_PHY_PWRDWN_2L, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN_MSK, + EA920_HSI0_PCIE_PHY_TEST_PWRDWN); + + return 0; +} + static const struct phy_ops fsd_phy0_ops =3D { .init =3D fsd_pcie_phy0_init, .reset =3D fsd_pcie_phy0_reset, @@ -410,6 +629,12 @@ static const struct phy_ops fsd_phy1_ops =3D { .owner =3D THIS_MODULE, }; =20 +static const struct phy_ops exynosautov920_phy_ops =3D { + .init =3D exynosautov920_pcie_phy_init, + .exit =3D exynosautov920_pcie_phy_exit, + .owner =3D THIS_MODULE, +}; + static const struct of_device_id exynos_pcie_phy_match[] =3D { { .compatible =3D "samsung,exynos5433-pcie-phy", @@ -423,6 +648,10 @@ static const struct of_device_id exynos_pcie_phy_match= [] =3D { .compatible =3D "tesla,fsd-pcie-phy1", .data =3D &fsd_phy1_ops, }, + { + .compatible =3D "samsung,exynosautov920-pcie-phy", + .data =3D &exynosautov920_phy_ops, + }, {}, }; =20 @@ -468,6 +697,8 @@ static int exynos_pcie_phy_probe(struct platform_device= *pdev) =20 exynos_phy->pcs_base =3D devm_platform_ioremap_resource(pdev, 1); =20 + of_property_read_u32(dev->of_node, "num-lanes", &exynos_phy->num_lanes); + phy_set_drvdata(generic_phy, exynos_phy); phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); =20 --=20 2.45.2