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Fri, 26 Sep 2025 00:29:47 -0700 (PDT) From: Anand Moon To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v1 2/5] PCI: tegra: Simplify clock handling by using clk_bulk*() functions Date: Fri, 26 Sep 2025 12:57:43 +0530 Message-ID: <20250926072905.126737-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250926072905.126737-1-linux.amoon@gmail.com> References: <20250926072905.126737-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the driver acquires clocks and prepare/enable/disable/unprepare the clocks individually thereby making the driver complex to read. The driver can be simplified by using the clk_bulk*() APIs. Use: - devm_clk_bulk_get() API to acquire all the clocks - clk_bulk_prepare_enable() to prepare/enable clocks - clk_bulk_disable_unprepare() APIs to disable/unprepare them in bulk Following change also removes the legacy has_cml_clk flag and its associated conditional logic. Instead, the driver now relies on the clock definitions = from the device tree to determine the correct clock sequencing. This reduces hardcoded dependencies and improves the driver's maintainabili= ty. Cc: Thierry Reding Cc: Jon Hunter Signed-off-by: Anand Moon --- v1: Switch from devm_clk_bulk_get_all() -> devm_clk_bulk_get() with fix clks array. nvidia,tegra20-pcie and nvidia,tegra186-pcie uses three clocks pex, afi, pll_e where as nvidia,tegra30-pcie, nvidia,tegra124-pcie, nvidia,tegra210-pcie uses four clks pex, afi, pll_e, cml --- --- drivers/pci/controller/pci-tegra.c | 100 +++++++++++++---------------- 1 file changed, 45 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 467ddc701adc..07a61d902eae 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -287,6 +287,8 @@ struct tegra_pcie_port_soc { struct tegra_pcie_soc { unsigned int num_ports; const struct tegra_pcie_port_soc *ports; + const char * const *clk_names; + unsigned int num_clks; unsigned int msi_base_shift; unsigned long afi_pex2_ctrl; u32 pads_pll_ctl; @@ -297,7 +299,6 @@ struct tegra_pcie_soc { bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; - bool has_cml_clk; bool has_gen2; bool force_pca_enable; bool program_uphy; @@ -330,10 +331,7 @@ struct tegra_pcie { =20 struct resource cs; =20 - struct clk *pex_clk; - struct clk *afi_clk; - struct clk *pll_e; - struct clk *cml_clk; + struct clk_bulk_data *clks; =20 struct reset_control *pex_rst; struct reset_control *afi_rst; @@ -1158,10 +1156,7 @@ static void tegra_pcie_power_off(struct tegra_pcie *= pcie) =20 reset_control_assert(pcie->afi_rst); =20 - clk_disable_unprepare(pcie->pll_e); - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); - clk_disable_unprepare(pcie->afi_clk); + clk_bulk_disable_unprepare(soc->num_clks, pcie->clks); =20 if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1202,35 +1197,16 @@ static int tegra_pcie_power_on(struct tegra_pcie *p= cie) } } =20 - err =3D clk_prepare_enable(pcie->afi_clk); + err =3D clk_bulk_prepare_enable(soc->num_clks, pcie->clks); if (err < 0) { - dev_err(dev, "failed to enable AFI clock: %d\n", err); + dev_err(dev, "filed to enable clocks: %d\n", err); goto powergate; } =20 - if (soc->has_cml_clk) { - err =3D clk_prepare_enable(pcie->cml_clk); - if (err < 0) { - dev_err(dev, "failed to enable CML clock: %d\n", err); - goto disable_afi_clk; - } - } - - err =3D clk_prepare_enable(pcie->pll_e); - if (err < 0) { - dev_err(dev, "failed to enable PLLE clock: %d\n", err); - goto disable_cml_clk; - } - reset_control_deassert(pcie->afi_rst); =20 return 0; =20 -disable_cml_clk: - if (soc->has_cml_clk) - clk_disable_unprepare(pcie->cml_clk); -disable_afi_clk: - clk_disable_unprepare(pcie->afi_clk); powergate: if (!dev->pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); @@ -1255,26 +1231,21 @@ static int tegra_pcie_clocks_get(struct tegra_pcie = *pcie) { struct device *dev =3D pcie->dev; const struct tegra_pcie_soc *soc =3D pcie->soc; + int ret, i; =20 - pcie->pex_clk =3D devm_clk_get(dev, "pex"); - if (IS_ERR(pcie->pex_clk)) - return PTR_ERR(pcie->pex_clk); - - pcie->afi_clk =3D devm_clk_get(dev, "afi"); - if (IS_ERR(pcie->afi_clk)) - return PTR_ERR(pcie->afi_clk); + pcie->clks =3D devm_kcalloc(dev, soc->num_clks, sizeof(*pcie->clks), + GFP_KERNEL); + if (!pcie->clks) + return -ENOMEM; =20 - pcie->pll_e =3D devm_clk_get(dev, "pll_e"); - if (IS_ERR(pcie->pll_e)) - return PTR_ERR(pcie->pll_e); + for (i =3D 0; i < soc->num_clks; i++) + pcie->clks[i].id =3D soc->clk_names[i]; =20 - if (soc->has_cml_clk) { - pcie->cml_clk =3D devm_clk_get(dev, "cml"); - if (IS_ERR(pcie->cml_clk)) - return PTR_ERR(pcie->cml_clk); - } + ret =3D devm_clk_bulk_get(dev, soc->num_clks, pcie->clks); + if (ret) + dev_err(dev, "failed to get PCIe clocks: %d\n", ret); =20 - return 0; + return ret; } =20 static int tegra_pcie_resets_get(struct tegra_pcie *pcie) @@ -2335,9 +2306,17 @@ static const struct tegra_pcie_port_soc tegra20_pcie= _ports[] =3D { { .pme.turnoff_bit =3D 8, .pme.ack_bit =3D 10 }, }; =20 +static const char * const tegra20_pcie_clks[] =3D { + "pex", + "afi", + "pll_e", +}; + static const struct tegra_pcie_soc tegra20_pcie =3D { .num_ports =3D 2, .ports =3D tegra20_pcie_ports, + .clk_names =3D tegra20_pcie_clks, + .num_clks =3D ARRAY_SIZE(tegra20_pcie_clks), .msi_base_shift =3D 0, .pads_pll_ctl =3D PADS_PLL_CTL_TEGRA20, .tx_ref_sel =3D PADS_PLL_CTL_TXCLKREF_DIV10, @@ -2345,7 +2324,6 @@ static const struct tegra_pcie_soc tegra20_pcie =3D { .has_pex_clkreq_en =3D false, .has_pex_bias_ctrl =3D false, .has_intr_prsnt_sense =3D false, - .has_cml_clk =3D false, .has_gen2 =3D false, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2356,6 +2334,13 @@ static const struct tegra_pcie_soc tegra20_pcie =3D { .ectl.enable =3D false, }; =20 +static const char * const tegra30_pcie_clks[] =3D { + "pex", + "afi", + "pll_e", + "cml", +}; + static const struct tegra_pcie_port_soc tegra30_pcie_ports[] =3D { { .pme.turnoff_bit =3D 0, .pme.ack_bit =3D 5 }, { .pme.turnoff_bit =3D 8, .pme.ack_bit =3D 10 }, @@ -2365,6 +2350,8 @@ static const struct tegra_pcie_port_soc tegra30_pcie_= ports[] =3D { static const struct tegra_pcie_soc tegra30_pcie =3D { .num_ports =3D 3, .ports =3D tegra30_pcie_ports, + .clk_names =3D tegra30_pcie_clks, + .num_clks =3D ARRAY_SIZE(tegra30_pcie_clks), .msi_base_shift =3D 8, .afi_pex2_ctrl =3D 0x128, .pads_pll_ctl =3D PADS_PLL_CTL_TEGRA30, @@ -2374,7 +2361,6 @@ static const struct tegra_pcie_soc tegra30_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D false, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2388,6 +2374,8 @@ static const struct tegra_pcie_soc tegra30_pcie =3D { static const struct tegra_pcie_soc tegra124_pcie =3D { .num_ports =3D 2, .ports =3D tegra20_pcie_ports, + .clk_names =3D tegra30_pcie_clks, + .num_clks =3D ARRAY_SIZE(tegra30_pcie_clks), .msi_base_shift =3D 8, .pads_pll_ctl =3D PADS_PLL_CTL_TEGRA30, .tx_ref_sel =3D PADS_PLL_CTL_TXCLKREF_BUF_EN, @@ -2395,7 +2383,6 @@ static const struct tegra_pcie_soc tegra124_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D true, .force_pca_enable =3D false, .program_uphy =3D true, @@ -2409,6 +2396,8 @@ static const struct tegra_pcie_soc tegra124_pcie =3D { static const struct tegra_pcie_soc tegra210_pcie =3D { .num_ports =3D 2, .ports =3D tegra20_pcie_ports, + .clk_names =3D tegra30_pcie_clks, + .num_clks =3D ARRAY_SIZE(tegra30_pcie_clks), .msi_base_shift =3D 8, .pads_pll_ctl =3D PADS_PLL_CTL_TEGRA30, .tx_ref_sel =3D PADS_PLL_CTL_TXCLKREF_BUF_EN, @@ -2418,7 +2407,6 @@ static const struct tegra_pcie_soc tegra210_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D true, .has_gen2 =3D true, .force_pca_enable =3D true, .program_uphy =3D true, @@ -2450,6 +2438,8 @@ static const struct tegra_pcie_port_soc tegra186_pcie= _ports[] =3D { static const struct tegra_pcie_soc tegra186_pcie =3D { .num_ports =3D 3, .ports =3D tegra186_pcie_ports, + .clk_names =3D tegra20_pcie_clks, + .num_clks =3D ARRAY_SIZE(tegra20_pcie_clks), .msi_base_shift =3D 8, .afi_pex2_ctrl =3D 0x19c, .pads_pll_ctl =3D PADS_PLL_CTL_TEGRA30, @@ -2459,7 +2449,6 @@ static const struct tegra_pcie_soc tegra186_pcie =3D { .has_pex_clkreq_en =3D true, .has_pex_bias_ctrl =3D true, .has_intr_prsnt_sense =3D true, - .has_cml_clk =3D false, .has_gen2 =3D true, .force_pca_enable =3D false, .program_uphy =3D false, @@ -2651,6 +2640,7 @@ static void tegra_pcie_remove(struct platform_device = *pdev) static int tegra_pcie_pm_suspend(struct device *dev) { struct tegra_pcie *pcie =3D dev_get_drvdata(dev); + const struct tegra_pcie_soc *soc =3D pcie->soc; struct tegra_pcie_port *port; int err; =20 @@ -2672,7 +2662,7 @@ static int tegra_pcie_pm_suspend(struct device *dev) } =20 reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); + clk_bulk_disable_unprepare(soc->num_clks, pcie->clks); =20 if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); @@ -2686,6 +2676,7 @@ static int tegra_pcie_pm_suspend(struct device *dev) static int tegra_pcie_pm_resume(struct device *dev) { struct tegra_pcie *pcie =3D dev_get_drvdata(dev); + const struct tegra_pcie_soc *soc =3D pcie->soc; int err; =20 err =3D tegra_pcie_power_on(pcie); @@ -2706,9 +2697,9 @@ static int tegra_pcie_pm_resume(struct device *dev) if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_enable_msi(pcie); =20 - err =3D clk_prepare_enable(pcie->pex_clk); + err =3D clk_bulk_prepare_enable(soc->num_clks, pcie->clks); if (err) { - dev_err(dev, "failed to enable PEX clock: %d\n", err); + dev_err(dev, "failed to enable clock: %d\n", err); goto pex_dpd_enable; } =20 @@ -2729,7 +2720,6 @@ static int tegra_pcie_pm_resume(struct device *dev) =20 disable_pex_clk: reset_control_assert(pcie->pex_rst); - clk_disable_unprepare(pcie->pex_clk); pex_dpd_enable: pinctrl_pm_select_idle_state(dev); poweroff: --=20 2.50.1