From nobody Wed Oct 1 22:37:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FFEF1DF75C; Fri, 26 Sep 2025 14:33:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897209; cv=none; b=RFtRX7yFk54CyLDjxH+yAc8gW0jgT82YZc8RjiWiz1fyXDK9Je4Kaw8UECYH8LuLkNvFjwFrM/0RGP8TpxVFtsjY3U2wvS6lUoS+SFQNs6vhrCH3peuSlDLN+6GRpQgzX6JCkSrstUNS1XxxDeT3zMx70S+Tek0Yog0w1QnLyJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897209; c=relaxed/simple; bh=BrLRY240+mmqBOHm/sMgW8G1cM6lFECM17Bu2MS+usE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=efVc3ZASbFz+m17MJJwDOqzmeC4o2SlHhXxUDpxo2V0L66HVjlRzDVtvY/i6tyxP9zwOuCmSpDbgd7KAE9FCTqKENEGimcq5Re+iqNIAyM5/GWihchb3ciqNoq5GwPObZOP1Vv6JkmX+EW/zQoJLV+87NH43zVjj7mNKAkYvbL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iXSlxW7k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iXSlxW7k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB05CC113D0; Fri, 26 Sep 2025 14:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758897207; bh=BrLRY240+mmqBOHm/sMgW8G1cM6lFECM17Bu2MS+usE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iXSlxW7kRdi2A1xi1lXCTGA8zaPhnVmJ0WvMwm7y/JG12KTa8Adi225Bob2Gf+4Zb ZLPYb6YziDJ5bQWwdWHrYinHzq5yLitRIumEhYA5QeT4u+dRAaVPoj4y60vH27u35k lSMCtvUh04Pu+157lB4UGr0kGRlwvFK84QDfg5uCfCkeOI9PhAsPcbgIrIOO7nCONZ aN9LsLRL4eg4zohg4VV1V4e1PLiYRiXBrIsBnUCId6Y90X4GbljUyL0TCHcDDxhgK3 7exQstAUvwJxhq36F83R2L8XuZEUvk1DzpJyM/Ohqo6dZERtG4kRjJBxuhM6HLAsof CUJK8NcXotqQQ== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC 1/5] dt-bindings: pinctrl: add polarfire soc iomux0 pinmux Date: Fri, 26 Sep 2025 15:33:09 +0100 Message-ID: <20250926-polo-jailhouse-aef50bf71c56@spud> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250926-manpower-glacial-e9756c82b427@spud> References: <20250926-manpower-glacial-e9756c82b427@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4122; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=gAbuGS8OaMl8BEtZC/wqb99I6dMe5gsmkDpWS+Cne4w=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBnXlqjs0f541NjI8Hz7ydLPk3a5LnVMW9Ks7F8dLb/2W uCP+IblHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIyXKGX0zSTXNnBYbHuz3J v1tVsnvTErc4y8OHVNffXMzLeq4iexfDP+USnWnZ191mGHE97JNLZipe9lWp5oHxrKh6zydl80I aGQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either MSS (multiprocessor subsystem) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Signed-off-by: Conor Dooley --- .../microchip,mpfs-pinctrl-iomux0.yaml | 77 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 15 ++++ 2 files changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpf= s-pinctrl-iomux0.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinct= rl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-p= inctrl-iomux0.yaml new file mode 100644 index 000000000000..779348304956 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomu= x0.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley + +description: + iomux0 is responsible for routing some functions to either the FPGA fabr= ic, + or to MSSIOs. It only performs muxing, and has no IO configuration role,= as + fabric IOs are configured separately and just routing a function to MSSI= Os is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + allOf: + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. The upper 16 bits of the value represent the func= tion + and the lower 16 bits where it is routed - 0 is to an MSSIO and = 1 to + the fabric. Which bit controls which function is described in the + register map in section MSS/pfsoc_mss_top_sysreg.htm#IOMUX0_CR. + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define MPFS_PINFUNC(pin, func) (((pin) << 16) | (func)) + + soc { + pinctrl@200 { + compatible =3D "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + + spi0_mssio: spi0-mssio-pins { + pinmux =3D ; + }; + + spi0_fabric: spi0-fabric-pins { + pinmux =3D ; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 1ab691db8795..1b737a3fcd33 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -18,10 +18,17 @@ properties: items: - const: microchip,mpfs-mss-top-sysreg - const: syscon + - const: simple-mfd =20 reg: maxItems: 1 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#reset-cells': description: The AHB/AXI peripherals on the PolarFire SoC have reset support, so @@ -31,6 +38,14 @@ properties: of PolarFire clock/reset IDs. const: 1 =20 + pinctrl@200: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + + pinctrl@204: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + required: - compatible - reg --=20 2.47.3 From nobody Wed Oct 1 22:37:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39CA20F067; Fri, 26 Sep 2025 14:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897211; cv=none; b=upujGR6WjGXvxqVnoG3SecqBz2r9CgtZe5TWc+D1fuJpI5WI1BjlNFnsamk95h06A4nUB1ccdIcxaJ2C57qYSUCEYgXbHC/F83fID/ExbZU/4PDwx3M/rez1mKV2ixBlduhK4vCsHlMTKuOUiqAkZ5022ikDQWdAb2h2woAFmUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897211; c=relaxed/simple; bh=MKaeoxAh1CI3sA7jOxBPksZc2blSaWDWwriebqE3Zoc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JFPzWRcqw6SJlNMOnJsOUupT5BdsoaVkIux0zIgTOsU6gYuH8VXRNicb0MpJi5Tlb5vn29Q0H7pqZHiluFv7/io99aQrLMUej9go2Pv3pDqkA38st48rhtV9tay3iRJJw1duJCR+TUFse9Jl82UIPvwhCBxTiD9TtMjQPFsKK6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cvLY8jQS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cvLY8jQS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4576C4CEF4; Fri, 26 Sep 2025 14:33:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758897209; bh=MKaeoxAh1CI3sA7jOxBPksZc2blSaWDWwriebqE3Zoc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cvLY8jQSgfr9cKQjSe7ujETaXlkOewz2I6IUP83GtCnylX45NFlLVZO8OoHIvjUps Cjulinzt2uqgxwk8fkH9pNY6DiqhoLb/S9mRNTBk4Koop99RUaCmVDRuLv+kZj7xAt wCOEhiVQOi7plaHkzBqdjB+vn2baRUoKozqiNElTaBPxTy8NSYNbSVhaqfl+2K+lS0 X5dQ/lMG6zVMEHzdkFNjab2M2O1SpmW/larRXZRGthOs6vOjFXBYGsPxtLusTcZ9uG 86lZtPeIzXOBVsheXwvTkcVjYfe4XycAtnRKYxsRBoOQxjZAAu78DW/RNPBjg2vDyt qOwsWaDpQ/nSg== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC 2/5] dt-bindings: pinctrl: add pic64gx "gpio2" pinmux Date: Fri, 26 Sep 2025 15:33:10 +0100 Message-ID: <20250926-gilled-muppet-6ac08937cea6@spud> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250926-manpower-glacial-e9756c82b427@spud> References: <20250926-manpower-glacial-e9756c82b427@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3794; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=whSSbDhJyexL6gok/iwOo1IqEtRu9dtNf4oF4w/Mry8=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBnXlqiI37yb5mf4sOPrD9/JKd8i9O99CfjOIblvg5OQm sFHq4siHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiI9GZGhq+xfG8W+LV1zH51 4GLqa7OzQdVx5exLbLxaD21L4o4ufMPwz/BHxPGZFly3SqWCXt9ObVjF9NpD9KpIjZb4nu2bEnl NWQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Currently there is no documentation about what each bit actually does that is publicly available, nor (I believe) what pins are affected. That info is as follows: pin role (1/0) --- ---------- E14 MAC_0_MDC/GPIO_2_0 E15 MAC_0_MDIO/GPIO_2_1 F16 MAC_1_MDC/GPIO_2_2 F17 MAC_1_MDIO/GPIO_2_3 D19 SPI_0_CLK/GPIO_2_4 B18 SPI_0_SS0/GPIO_2_5 B10 CAN_0_RXBUS/GPIO_2_6 C14 PCIE_PERST_2#/GPIO_2_7 E18 PCIE_WAKE#/GPIO_2_8 D18 PCIE_PERST_1#/GPIO_2_9 E19 SPI_0_DO/GPIO_2_10 C7 SPI_0_DI/GPIO_2_11 D6 QSPI_SS0/GPIO_2_12 D7 QSPI_CLK (B)/GPIO_2_13 C9 QSPI_DATA0/GPIO_2_14 C10 QSPI_DATA1/GPIO_2_15 A5 QSPI_DATA2/GPIO_2_16 A6 QSPI_DATA3/GPIO_2_17 D8 MMUART_3_RXD/GPIO_2_18 D9 MMUART_3_TXD/GPIO_2_19 B8 MMUART_4_RXD/GPIO_2_20 A8 MMUART_4_TXD/GPIO_2_21 C12 CAN_1_TXBUS/GPIO_2_22 B12 CAN_1_RXBUS/GPIO_2_23 A11 CAN_0_TX_EBL_N/GPIO_2_24 A10 CAN_1_TX_EBL_N/GPIO_2_25 D11 MMUART_2_RXD/GPIO_2_26 C11 MMUART_2_TXD/GPIO_2_27 B9 CAN_0_TXBUS/GPIO_2_28 Signed-off-by: Conor Dooley --- .../microchip,pic64gx-pinctrl-gpio2.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic= 64gx-pinctrl-gpio2.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pi= nctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic6= 4gx-pinctrl-gpio2.yaml new file mode 100644 index 000000000000..be7d4b1948dc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-g= pio2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux=20 + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + allOf: + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. The upper 16 bits of the value represent the pin + and the lower 16 bits determine which function is routed there. + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define PIC64GX_PINFUNC(pin, func) (((pin) << 16) | (func)) + + soc { + pinctrl@f00 { + compatible =3D "microchip,pic64gx-pinctrl-gpio2"; + reg =3D <0xf00 0x4>; + pinctrl-use-default; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_= gpio2>, + <&mmuart3_gpio2>, <&mmuart4_gpio2>, <&can1_gpio2>, <&can0_gpio= 2>, + <&mmuart2_gpio2>; + + mdio0_gpio: gpio0-gpio-pins { + pinmux =3D , ; + }; + + mdio0_mdio: mdio0-mdio-pins { + pinmux =3D , ; + }; + }; + }; + +... --=20 2.47.3 From nobody Wed Oct 1 22:37:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A485218ADD; Fri, 26 Sep 2025 14:33:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897212; cv=none; b=fFi4L84gz24zNDcSD9IzVqC+tKwToqMPmA/zJ+VUGMDyzxmkFqPFzo11ZgkJwG+TODILmiyx2Pr2mVQV5JQ0ptXdOKhUvvVCsfnv4Qe58+Pk2ZcZ0IcJcNwdR6TbCcp8t/jQTWzqHwsrMoUf12LTN61aPxoY//Fm2fdH+sI4ofM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897212; c=relaxed/simple; bh=cxtJAwcSroUFWX+p132OdjkCtTK4tzieiQjBgjmy2pY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y0YeVGpgVfMI9er7mS77gmaz0PZu19ecMiiCff0rOqkNgWqZgM9TizofUAPpVZHXTnjovnxvut7gRtKrgVmhsElkRRHlkCaH/XS9WPXUwy2u3IY3P1KAsSkWE2/ZFeEG7s3Pn0KlnvLd2s955VgftCoTdm2v318tFJ6Ev8smcfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WUJv/JqQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WUJv/JqQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC44BC4CEF7; Fri, 26 Sep 2025 14:33:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758897211; bh=cxtJAwcSroUFWX+p132OdjkCtTK4tzieiQjBgjmy2pY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WUJv/JqQFFSGzDySxaNkF4D1HU2Xa4CqOLWGOCKpGMYY04qrTPbpz8tp3IAtvJk7z qwcjcIe2nLyDfYUGfmlVc/XEbUGXuJ6ZRP24cXDHy81QLb8ourQSYdHECnipaB852h 4Xitp4WbyQi+gRPmosMNs21r7PEaw5y7ey1RpsiCnuronSCuT7dAXyj+DDMxB4k8Ip veQVZoagmP0VnwzhIT7k7c9vZn1DZ7MUewvQhh4JS6l0c6wakY7osX9Wq1tJsCHxOs xceH8+zOP4o5+XFnxcCsjWzwTVqWuwbNF6mPAf90K6G4H39IgUgfcy7u/G1NAUjybl Bmf/1VxNXcm3g== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC 3/5] pinctrl: add polarfire soc iomux0 pinmux driver Date: Fri, 26 Sep 2025 15:33:11 +0100 Message-ID: <20250926-unshackle-jury-79f701f97e94@spud> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250926-manpower-glacial-e9756c82b427@spud> References: <20250926-manpower-glacial-e9756c82b427@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10112; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=3Ua9rGDiZ78KGESuIEYgHMwQRlK1a6Eq+e6zOrIYK7g=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBnXlqi+5BLbsLPyjY1wg7nW06e7p30IK7QM+fjw2jaNL /M5Xq9s7ihlYRDjYpAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEBJoZGfblm7Smbt1qa3vU 5my269wLGs7rJWLWeGxwTbpdpN4z5Twjw9L42d9fKF3d8fD48pX38k1s65i+GEpVqR7c/czN+Ky OOh8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either MSS (multiprocessor subsystem) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Add a driver for it. Signed-off-by: Conor Dooley --- .../microchip,mpfs-mss-top-sysreg.yaml | 2 +- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mpfs-iomux0.c | 252 ++++++++++++++++++ 4 files changed, 261 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/pinctrl-mpfs-iomux0.c diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 1b737a3fcd33..cb5784ec5ac5 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -55,7 +55,7 @@ additionalProperties: false examples: - | syscon@20002000 { - compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mf= d"; reg =3D <0x20002000 0x1000>; #reset-cells =3D <1>; }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 33db9104df17..f85ccbc2a0e2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -472,6 +472,13 @@ config PINCTRL_PISTACHIO help This support pinctrl and GPIO driver for IMG Pistachio SoC. =20 +config PINCTRL_POLARFIRE_SOC + bool "Polarfire SoC pinctrl driver" + depends on ARCH_MICROCHIP + default y + help + This selects the pinctrl driver for Microchip Polarfire SoC. + config PINCTRL_RK805 tristate "Pinctrl and GPIO driver for RK805 PMIC" depends on MFD_RK8XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ac27e88677d1..8af119804f77 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_PALMAS) +=3D pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SCMI) +=3D pinctrl-scmi.o diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctr= l-mpfs-iomux0.c new file mode 100644 index 000000000000..93a17c9c299d --- /dev/null +++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define MPFS_PINCTRL_DT_FUNC_MASK GENMASK(3, 0); +#define MPFS_PINCTRL_DT_PIN_OFFSET 16 + +#define MPFS_PINCTRL_IOMUX0_REG 0x200 + +struct mpfs_iomux0_pinctrl_mux_config { + u8 pin; + u32 config; +}; + +struct mpfs_iomux0_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct mutex mutex; + struct pinctrl_desc desc; +}; + +static void mpfs_iomux0_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, st= ruct seq_file *seq, + unsigned int pin) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + + seq_printf(seq, "reg: %x, pin: %u ", MPFS_PINCTRL_IOMUX0_REG, pin); + + regmap_read(pctrl->regmap, MPFS_PINCTRL_IOMUX0_REG, &val); + val =3D (val & BIT(pin)) >> pin; + + seq_printf(seq, "val: %x\n", val); +} + +static int mpfs_iomux0_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_de= v, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev =3D pctrl->dev; + struct mpfs_iomux0_pinctrl_mux_config *pinmuxs; + struct pinctrl_map *map; + const char **grpnames; + const char *grpname; + int ret, i, npins; + unsigned int config, *pins; + + map =3D kcalloc(1, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + guard(mutex)(&pctrl->mutex); + + npins =3D of_property_count_u32_elems(np, "pinmux"); + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn\n", np); + return -EINVAL; + } + + grpnames =3D devm_kmalloc(dev, sizeof(*grpnames), GFP_KERNEL); + if (!grpnames) + return -ENOMEM; + + grpname =3D devm_kasprintf(dev, GFP_KERNEL, "%pOFn", np); + if (!grpname) + return -ENOMEM; + + *grpnames =3D grpname; + + pins =3D devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pinmuxs =3D devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) + return -ENOMEM; + + for (i =3D 0; i < npins; i++) { + ret =3D of_property_read_u32_index(np, "pinmux", i, &config); + if (ret) + return -EINVAL; + + pins[i] =3D config >> MPFS_PINCTRL_DT_PIN_OFFSET; + pinmuxs[i].config =3D config & MPFS_PINCTRL_DT_FUNC_MASK; + pinmuxs[i].pin =3D config >> MPFS_PINCTRL_DT_PIN_OFFSET; + } + + map->type =3D PIN_MAP_TYPE_MUX_GROUP; + map->data.mux.function =3D np->name; + map->data.mux.group =3D grpname; + + ret =3D pinctrl_generic_add_group(pctrl_dev, grpname, pins, npins, pinmux= s); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, = ret); + + ret =3D pinmux_generic_add_function(pctrl_dev, np->name, grpnames, 1, NUL= L); + if (ret < 0) { + pinctrl_utils_free_map(pctrl_dev, map, 1); + return dev_err_probe(dev, ret, "error adding function %s\n", np->name); + } + + *maps =3D map; + *num_maps =3D 1; + + return 0; +}; + +static struct pinctrl_ops mpfs_iomux0_pinctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .pin_dbg_show =3D mpfs_iomux0_pinctrl_dbg_show, + .dt_node_to_map =3D mpfs_iomux0_pinctrl_dt_node_to_map, + .dt_free_map =3D pinctrl_utils_free_map, +}; + +static int mpfs_iomux0_pinctrl_set_pin_func(struct mpfs_iomux0_pinctrl *pc= trl, u8 pin, u32 config) +{ + struct device *dev =3D pctrl->dev; + u32 state; + + state =3D config & MPFS_PINCTRL_DT_FUNC_MASK; + state <<=3D pin; + + dev_dbg(dev, "Setting pin %u reg %x offset %u func %x\n", pin, MPFS_PINCT= RL_IOMUX0_REG, pin, state); + + regmap_set_bits(pctrl->regmap, MPFS_PINCTRL_IOMUX0_REG, state); + + return 0; +} + +static int mpfs_iomux0_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsi= gned int fsel, unsigned int gsel) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + const struct group_desc *group; + struct mpfs_iomux0_pinctrl_mux_config *configs; + int ret =3D -EINVAL; + + group =3D pinctrl_generic_get_group(pctrl_dev, gsel); + if (!group) + return -EINVAL; + + configs =3D group->data; + + for (int i =3D 0; i < group->grp.npins; i++) { + u8 pin =3D configs[i].pin; + u32 config =3D configs[i].config; + + ret =3D mpfs_iomux0_pinctrl_set_pin_func(pctrl, pin, config); + } + + return ret; +} + +static const struct pinmux_ops mpfs_iomux0_pinctrl_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D mpfs_iomux0_pinctrl_set_mux, +}; + +static const struct pinctrl_pin_desc mpfs_iomux0_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "spi0"), + PINCTRL_PIN(1, "spi1"), + PINCTRL_PIN(2, "i2c0"), + PINCTRL_PIN(3, "i2c1"), + PINCTRL_PIN(4, "can0"), + PINCTRL_PIN(5, "can1"), + PINCTRL_PIN(6, "qspi"), + PINCTRL_PIN(7, "uart0"), + PINCTRL_PIN(8, "uart1"), + PINCTRL_PIN(9, "uart2"), + PINCTRL_PIN(10, "uart3"), + PINCTRL_PIN(11, "uart4"), + PINCTRL_PIN(12, "mdio0"), + PINCTRL_PIN(13, "mdio1"), + +}; + +static int mpfs_iomux0_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mpfs_iomux0_pinctrl *pctrl; + int ret; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(pctrl->regmap)) + dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap= \n"); + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D mpfs_iomux0_pinctrl_pins; + pctrl->desc.npins =3D ARRAY_SIZE(mpfs_iomux0_pinctrl_pins); + pctrl->desc.pctlops =3D &mpfs_iomux0_pinctrl_ops; + pctrl->desc.pmxops =3D &mpfs_iomux0_pinctrl_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + ret =3D devm_mutex_init(dev, &pctrl->mutex); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id mpfs_iomux0_pinctrl_of_match[] =3D { + { .compatible =3D "microchip,mpfs-pinctrl-iomux0" }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_iomux0_pinctrl_of_match); + +static struct platform_driver mpfs_iomux0_pinctrl_driver =3D { + .driver =3D { + .name =3D "mpfs-pinctrl-iomux0", + .of_match_table =3D mpfs_iomux0_pinctrl_of_match, + }, + .probe =3D mpfs_iomux0_pinctrl_probe, +}; +module_platform_driver(mpfs_iomux0_pinctrl_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.47.3 From nobody Wed Oct 1 22:37:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 396A921CC79; Fri, 26 Sep 2025 14:33:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897214; cv=none; b=HLvaXAn0koBNFDtxeiKUBhsktVuK5zsdWl+uhGUwR9bZUx3oxS+Zb36PiF8bF/FiOtPtrLsBQ1yNEvgyMFNCPCIeJhsuhUH+u3YdWMfgzAiBx6csWKLPpMmJYznqav3SvYcWL3VtPj4sF5CzLXGjsy9sw0rz/FgnNKBqQO8WwWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758897214; c=relaxed/simple; bh=ngk1ZvJx0G1wt33VLB3prZ5qrkv2guaMvCgsiOGDmhk=; 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a=openpgp-sha256; l=10969; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=5eY/QKf3BTB5TvZmK/rAP8gdhe2ajmpqm/CJwTEOZ68=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBnXlqjKxHxZUVXysS5dL2b+Bu65qSWVGV+FlwckV1uxH snlDtvcUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIlw9DH8U3ws+/3zVWEW5TX2 pfkmCfMOrl97aMJk702G8/MuqdR7PmJkmN6TpP3/udc3c08j8713PGTnrNlc1/O/YJep0MaZEVe duAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Add a driver for it. Signed-off-by: Conor Dooley --- .../microchip,pic64gx-pinctrl-gpio2.yaml | 2 +- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-pic64gx-gpio2.c | 283 ++++++++++++++++++ 4 files changed, 292 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/pinctrl-pic64gx-gpio2.c diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pi= nctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic6= 4gx-pinctrl-gpio2.yaml index be7d4b1948dc..6af7b67731d6 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-g= pio2.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-g= pio2.yaml @@ -16,7 +16,7 @@ description: =20 properties: compatible: - const: microchip,pic64gx-pinctrl-gpio2 + const: microchip,pic64gx-pinctrl-gpio2 =20 reg: maxItems: 1 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f85ccbc2a0e2..692eb577ed74 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -461,6 +461,13 @@ config PINCTRL_PIC32MZDA def_bool y if PIC32MZDA select PINCTRL_PIC32 =20 +config PINCTRL_PIC64GX + bool "pic64gx gpio2 pinctrl driver" + depends on ARCH_MICROCHIP + default y + help + This selects the pinctrl driver for gpio2 on pic64gx. + config PINCTRL_PISTACHIO bool "IMG Pistachio SoC pinctrl driver" depends on OF && (MIPS || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8af119804f77..5493628a9a47 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) +=3D pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_PALMAS) +=3D pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o +obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/pinc= trl-pic64gx-gpio2.c new file mode 100644 index 000000000000..b0607aad934c --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define PIC64GX_PINCTRL_DT_FUNC_MASK GENMASK(3, 0); +#define PIC64GX_PINCTRL_DT_PIN_OFFSET 16 + +#define PIC64GX_PINMUX_REG 0x0 + +static const struct regmap_config pic64gx_gpio2_pinctrl_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D 0x0, +}; + +struct pic64gx_gpio2_pinctrl_mux_config { + u8 pin; + u32 config; +}; + +struct pic64gx_gpio2_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct mutex mutex; + struct pinctrl_desc desc; +}; + +static void pic64gx_gpio2_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, = struct seq_file *seq, + unsigned int pin) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + u32 val; + + seq_printf(seq, "reg: %x, pin: %u ", PIC64GX_PINMUX_REG, pin); + + regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val); + val =3D (val & BIT(pin)) >> pin; + seq_printf(seq, "val: %x\n", val); +} + +static int pic64gx_gpio2_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_= dev, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + struct device *dev =3D pctrl->dev; + struct pic64gx_gpio2_pinctrl_mux_config *pinmuxs; + struct pinctrl_map *map; + const char **grpnames; + const char *grpname; + int ret, i, npins; + unsigned int config, *pins; + + map =3D kcalloc(1, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + guard(mutex)(&pctrl->mutex); + + npins =3D of_property_count_u32_elems(np, "pinmux"); + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn\n", np); + return -EINVAL; + } + + grpnames =3D devm_kmalloc(dev, sizeof(*grpnames), GFP_KERNEL); + if (!grpnames) + return -ENOMEM; + + grpname =3D devm_kasprintf(dev, GFP_KERNEL, "%pOFn", np); + if (!grpname) + return -ENOMEM; + + *grpnames =3D grpname; + + pins =3D devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pinmuxs =3D devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) + return -ENOMEM; + + for (i =3D 0; i < npins; i++) { + ret =3D of_property_read_u32_index(np, "pinmux", i, &config); + if (ret) + return -EINVAL; + + pins[i] =3D config >> PIC64GX_PINCTRL_DT_PIN_OFFSET; + pinmuxs[i].config =3D config & PIC64GX_PINCTRL_DT_FUNC_MASK; + pinmuxs[i].pin =3D config >> PIC64GX_PINCTRL_DT_PIN_OFFSET; + } + + map->type =3D PIN_MAP_TYPE_MUX_GROUP; + map->data.mux.function =3D np->name; + map->data.mux.group =3D grpname; + + ret =3D pinctrl_generic_add_group(pctrl_dev, grpname, pins, npins, pinmux= s); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, = ret); + + ret =3D pinmux_generic_add_function(pctrl_dev, np->name, grpnames, 1, NUL= L); + if (ret < 0) { + pinctrl_utils_free_map(pctrl_dev, map, 1); + return dev_err_probe(dev, ret, "error adding function %s\n", np->name); + } + + *maps =3D map; + *num_maps =3D 1; + + return 0; +}; + +static struct pinctrl_ops pic64gx_gpio2_pinctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .pin_dbg_show =3D pic64gx_gpio2_pinctrl_dbg_show, + .dt_node_to_map =3D pic64gx_gpio2_pinctrl_dt_node_to_map, + .dt_free_map =3D pinctrl_utils_free_map, +}; + +static int pic64gx_gpio2_pinctrl_set_pin_func(struct pic64gx_gpio2_pinctrl= *pctrl, u8 pin, u32 config) +{ + struct device *dev =3D pctrl->dev; + u32 func; + + func =3D config & PIC64GX_PINCTRL_DT_FUNC_MASK; + func <<=3D pin; + + dev_dbg(dev, "Setting pin %u reg: %x pin %u func %x\n", pin, PIC64GX_PINM= UX_REG, pin, func); + + regmap_set_bits(pctrl->regmap, PIC64GX_PINMUX_REG, func); + + return 0; +} + +static int pic64gx_gpio2_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, un= signed int fsel, unsigned int gsel) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + const struct group_desc *group; + struct pic64gx_gpio2_pinctrl_mux_config *configs; + int ret =3D -EINVAL; + + group =3D pinctrl_generic_get_group(pctrl_dev, gsel); + if (!group) + return -EINVAL; + + configs =3D group->data; + + for (int i =3D 0; i < group->grp.npins; i++) { + u8 pin =3D configs[i].pin; + u32 config =3D configs[i].config; + + ret =3D pic64gx_gpio2_pinctrl_set_pin_func(pctrl, pin, config); + } + + return ret; +} + +static const struct pinmux_ops pic64gx_gpio2_pinctrl_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D pic64gx_gpio2_pinctrl_set_mux, +}; + +static const struct pinctrl_pin_desc pic64gx_gpio2_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "gpio2 0"), + PINCTRL_PIN(1, "gpio2 1"), + PINCTRL_PIN(2, "gpio2 2"), + PINCTRL_PIN(3, "gpio2 3"), + PINCTRL_PIN(4, "gpio2 4"), + PINCTRL_PIN(5, "gpio2 5"), + PINCTRL_PIN(6, "gpio2 6"), + PINCTRL_PIN(7, "gpio2 7"), + PINCTRL_PIN(8, "gpio2 8"), + PINCTRL_PIN(9, "gpio2 9"), + PINCTRL_PIN(10, "gpio2 10"), + PINCTRL_PIN(11, "gpio2 11"), + PINCTRL_PIN(12, "gpio2 12"), + PINCTRL_PIN(13, "gpio2 13"), + PINCTRL_PIN(14, "gpio2 14"), + PINCTRL_PIN(15, "gpio2 15"), + PINCTRL_PIN(16, "gpio2 16"), + PINCTRL_PIN(17, "gpio2 17"), + PINCTRL_PIN(18, "gpio2 18"), + PINCTRL_PIN(19, "gpio2 19"), + PINCTRL_PIN(20, "gpio2 20"), + PINCTRL_PIN(21, "gpio2 21"), + PINCTRL_PIN(22, "gpio2 22"), + PINCTRL_PIN(23, "gpio2 23"), + PINCTRL_PIN(24, "gpio2 24"), + PINCTRL_PIN(25, "gpio2 25"), + PINCTRL_PIN(26, "gpio2 26"), + PINCTRL_PIN(27, "gpio2 27"), + PINCTRL_PIN(28, "gpio2 28"), + +}; + +static int pic64gx_gpio2_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pic64gx_gpio2_pinctrl *pctrl; + void __iomem *base; + int ret; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "Failed get resource\n"); + return PTR_ERR(base); + } + + pctrl->regmap =3D devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_pinctrl= _regmap_config); + if (IS_ERR(pctrl->regmap)) { + dev_err(dev, "Failed to map regmap\n"); + return PTR_ERR(pctrl->regmap); + } + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D pic64gx_gpio2_pinctrl_pins; + pctrl->desc.npins =3D ARRAY_SIZE(pic64gx_gpio2_pinctrl_pins); + pctrl->desc.pctlops =3D &pic64gx_gpio2_pinctrl_ops; + pctrl->desc.pmxops =3D &pic64gx_gpio2_pinctrl_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + ret =3D devm_mutex_init(dev, &pctrl->mutex); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id pic64gx_gpio2_pinctrl_of_match[] =3D { + { .compatible =3D "microchip,pic64gx-pinctrl-gpio2" }, + { } +}; +MODULE_DEVICE_TABLE(of, pic64gx_gpio2_pinctrl_of_match); + +static struct platform_driver pic64gx_gpio2_pinctrl_driver =3D { + .driver =3D { + .name =3D "pic64gx-pinctrl-gpio2", + .of_match_table =3D pic64gx_gpio2_pinctrl_of_match, + }, + .probe =3D pic64gx_gpio2_pinctrl_probe, +}; +module_platform_driver(pic64gx_gpio2_pinctrl_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.47.3 From nobody Wed Oct 1 22:37:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F4641E5710; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dpOsrrVj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EC25C116C6; Fri, 26 Sep 2025 14:33:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758897215; bh=QIhdLhWroE0KrBzK06zF9iZfWdc0NXhltR+LoAqz2Sc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dpOsrrVjL64Hj830iLNUO171D5ZXYF+i+78OhvNwtvZnH+9Qelsrp15G9NMBnrQaJ PhGmnPN2WEriuqYaTn87TFpCiXlQ9n7sN4u/6Gnj4dZH9OXAi3Rxzv55TGVIQyHc4x 5ix6xaG16qHOCjQTGHK++WgQIeCZPJwzE4pOEpgntVvEn2vmx+X0wg/d8ozj0oxkeC N/1x22eDvV+KA4f3llyknux413T0bXnhAHStvyN6bIzdjedNnwiT9aC5e23PLAPb2W uG7Iblnd8SwtHAREr/cllpfkuLxhA1NKhAR8SvIbIn8CyIpdDVaJE5GpRhhz6mahw/ /KNhmG5TOfBlg== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC 5/5] riscv: dts: microchip: add pinctrl nodes for iomux0 Date: Fri, 26 Sep 2025 15:33:13 +0100 Message-ID: <20250926-manhandle-elliptic-fe3693bae638@spud> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250926-manpower-glacial-e9756c82b427@spud> References: <20250926-manpower-glacial-e9756c82b427@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6241; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=OjPtl0hrmmQCBu1p1jeqReHlGPIYs4iZyh4c+2jtfkI=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBnXlqjOYuORnPvSmW9XyilN2d5Mtn0rNHtcl0tU6yy4+ yLn2MwrHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjI+WBGhpklZ7Oi7k1fbDDB 593Zpo+3s344XGpVWLQz792XZOX9iwUY/hcmzQq37pGzrhB4LTOxcssX/6yDqyV2B8Y6eUoJ3r4 RywcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Signed-off-by: Conor Dooley --- This is in RFC state, the commented out perpiherals use a child to iomux0, and the patch ultimately adding the pinctrl dts nodes will add both iomux0 and its child. Please ignore them for now. That's also the reason for no commit message yet, since the final thing will be different. --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 56 +++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 1 - .../boot/dts/microchip/mpfs-pinctrl.dtsi | 117 ++++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 9 ++ 4 files changed, 182 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a6dda55a2d1d..4cf8fd1dd24d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -1,6 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 +#include "mpfs.dtsi" +#include "mpfs-pinctrl.dtsi" + / { compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; @@ -63,6 +66,15 @@ refclk_ccc: cccrefclk { }; }; =20 +&can0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&can0_fabric>; +}; + +&can1 { +// pinctrl-names =3D "default"; +}; + &ccc_nw { clocks =3D <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>; @@ -70,3 +82,47 @@ &ccc_nw { "dll0_ref", "dll1_ref"; status =3D "okay"; }; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_fabric>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_fabric>; +}; + +&mmuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmuart1_fabric>; +}; + +&mmuart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmuart2_fabric>; +}; + +&mmuart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmuart3_fabric>; +}; + +&mmuart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmuart4_fabric>; +}; + +&qspi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qspi_fabric>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_fabric>; +}; + +&spi1 { +// pinctrl-names =3D "default"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f80df225f72b..3c4d5f576e86 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,6 @@ =20 /dts-v1/; =20 -#include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" #include #include diff --git a/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi b/arch/riscv/b= oot/dts/microchip/mpfs-pinctrl.dtsi new file mode 100644 index 000000000000..1e4d55bd786f --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define MPFS_PINFUNC(pin, func) (((pin) << 16) | (func)) + +&iomux0 { + spi0_mssio: spi0-mssio-pins { + pinmux =3D ; + }; + + spi0_fabric: spi0-fabric-pins { + pinmux =3D ; + }; + + spi1_mssio: spi1-mssio-pins { + pinmux =3D ; + }; + + spi1_fabric: spi1-fabric-pins { + pinmux =3D ; + }; + + i2c0_mssio: i2c0-mssio-pins { + pinmux =3D ; + }; + + i2c0_fabric: i2c0-fabric-pins { + pinmux =3D ; + }; + + i2c1_mssio: i2c1-mssio-pins { + pinmux =3D ; + }; + + i2c1_fabric: i2c1-fabric-pins { + pinmux =3D ; + }; + + can0_mssio: can0-mssio-pins { + pinmux =3D ; + }; + + can0_fabric: can0-fabric-pins { + pinmux =3D ; + }; + + can1_mssio: can1-mssio-pins { + pinmux =3D ; + }; + + can1_fabric: can1-fabric-pins { + pinmux =3D ; + }; + + qspi_mssio: qspi-mssio-pins { + pinmux =3D ; + }; + + qspi_fabric: qspi-fabric-pins { + pinmux =3D ; + }; + + mmuart0_mssio: mmuart0-mssio-pins { + pinmux =3D ; + }; + + mmuart0_fabric: mmuart0-fabric-pins { + pinmux =3D ; + }; + + mmuart1_mssio: mmuart1-mssio-pins { + pinmux =3D ; + }; + + mmuart1_fabric: mmuart1-fabric-pins { + pinmux =3D ; + }; + + mmuart2_mssio: mmuart2-mssio-pins { + pinmux =3D ; + }; + + mmuart2_fabric: mmuart2-fabric-pins { + pinmux =3D ; + }; + + mmuart3_mssio: mmuart3-mssio-pins { + pinmux =3D ; + }; + + mmuart3_fabric: mmuart3-fabric-pins { + pinmux =3D ; + }; + + mmuart4_mssio: mmuart4-mssio-pins { + pinmux =3D ; + }; + + mmuart4_fabric: mmuart4-fabric-pins { + pinmux =3D ; + }; + + mdio0_mssio: mdio0-mssio-pins { + pinmux =3D ; + }; + + mdio0_fabric: mdio0-fabric-pins { + pinmux =3D ; + }; + + mdio1_mssio: mdio1-mssio-pins { + pinmux =3D ; + }; + + mdio1_fabric: mdio1-fabric-pins { + pinmux =3D ; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 5c2963e269b8..0a0cfd3d3054 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -254,7 +254,16 @@ pdma: dma-controller@3000000 { mss_top_sysreg: syscon@20002000 { compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg =3D <0x0 0x20002000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; #reset-cells =3D <1>; + + iomux0: pinctrl@200 { + compatible =3D "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + pinctrl-use-default; + + }; }; =20 sysreg_scb: syscon@20003000 { --=20 2.47.3