From nobody Wed Oct 1 23:30:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F858284881; Fri, 26 Sep 2025 20:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758916863; cv=none; b=MZbtXV3Jzw19fG2NpvpkphMcVEljRgREBLpuLYebRok6w0X8aIoayrGRz+DDeSEssne+JjsGKY0tnu1IjYcArXrz8y1ku+l0NtYq7IqahGYViiTe6CH2bApxzDcZXbxyRc32tZJEeZjyjMHUb39UjkxHXu8PtF7Nfisc7NAVv5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758916863; c=relaxed/simple; bh=VrScBIYSfKRZfjLBhdHvKQ8ivF27K2sZ3AX/FRfiGJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZT1D7ozTwMgqBESWC/UIHVHJXQveFbNKfmP9iw5r1SdQeYnlF6966ffEtG4VxF4lr/Kh9TzZjz0KIXv9FOlnqyX8Xrj0dVkGWwq38PACWv5b/rbafyaYk0xMgWM2KZ5b1w75QvwxWmwsEnlBFCi4+7z39bk+HmN/kVPw+NU+2ro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lde444+l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lde444+l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB54DC4CEF8; Fri, 26 Sep 2025 20:01:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758916862; bh=VrScBIYSfKRZfjLBhdHvKQ8ivF27K2sZ3AX/FRfiGJg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lde444+lFoMFHUN+yev8G5Lb+iE9bK2hslCVKWhN+EfgzC8dc3u0Judk6ZnQuLlHx r2zKuufhDg/WCLeKw47ZlB4i8V7bbvNCD/oSA4yRcVwa1kuYsb9GRW8/Up8LPwZv34 5dFy+JjRvu/MHnIy6tUTmheZyRp3WQBlte1pcLAlE6loFH3ybn6XBK9BbhfWVy8jYa 6FZoL+3+7B1dscUHsD7/YiuInDNCzaE15jD9sP6nTfg/Wd0VwlVblbAxyOxBBLBzgi EwrG24FTzUsJsjbCTqBIOYGfIEeVlWvl/Wr8DSrHD8iEvMBF/aJzPyUdwbU8Hft7hf EC7B9gkOm3KzA== From: "Rob Herring (Arm)" Date: Fri, 26 Sep 2025 15:00:48 -0500 Subject: [PATCH v3 1/2] dt-bindings: npu: Add Arm Ethos-U65/U85 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250926-ethos-v3-1-6bd24373e4f5@kernel.org> References: <20250926-ethos-v3-0-6bd24373e4f5@kernel.org> In-Reply-To: <20250926-ethos-v3-0-6bd24373e4f5@kernel.org> To: Tomeu Vizoso , Krzysztof Kozlowski , Conor Dooley , Oded Gabbay , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Robin Murphy , Steven Price , Daniel Stone Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org X-Mailer: b4 0.15-dev Add a binding schema for Arm Ethos-U65/U85 NPU. The Arm Ethos-U NPUs are designed for edge AI inference applications. Signed-off-by: Rob Herring (Arm) Reviewed-by: Frank Li --- .../devicetree/bindings/npu/arm,ethos.yaml | 79 ++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/Documentation/devicetree/bindings/npu/arm,ethos.yaml b/Documen= tation/devicetree/bindings/npu/arm,ethos.yaml new file mode 100644 index 000000000000..716c4997f976 --- /dev/null +++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/arm,ethos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Ethos U65/U85 + +maintainers: + - Rob Herring + +description: > + The Arm Ethos-U NPUs are designed for IoT inference applications. The NP= Us + can accelerate 8-bit and 16-bit integer quantized networks: + + Transformer networks (U85 only) + Convolutional Neural Networks (CNN) + Recurrent Neural Networks (RNN) + + Further documentation is available here: + + U65 TRM: https://developer.arm.com/documentation/102023/ + U85 TRM: https://developer.arm.com/documentation/102685/ + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx93-npu + - const: arm,ethos-u65 + - items: + - {} + - const: arm,ethos-u85 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: apb + + power-domains: + maxItems: 1 + + sram: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + + npu@4a900000 { + compatible =3D "fsl,imx93-npu", "arm,ethos-u65"; + reg =3D <0x4a900000 0x1000>; + interrupts =3D ; + power-domains =3D <&mlmix>; + clocks =3D <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + clock-names =3D "core", "apb"; + sram =3D <&sram>; + }; +... --=20 2.51.0