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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ5PEPF000001E8.mail.protection.outlook.com (10.167.242.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.9 via Frontend Transport; Thu, 25 Sep 2025 22:36:05 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 25 Sep 2025 15:36:03 -0700 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v12 07/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Date: Thu, 25 Sep 2025 17:34:22 -0500 Message-ID: <20250925223440.3539069-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925223440.3539069-1-terry.bowman@amd.com> References: <20250925223440.3539069-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E8:EE_|SJ1PR12MB6217:EE_ X-MS-Office365-Filtering-Correlation-Id: d5cca780-9e50-4d1d-0f76-08ddfc83ea57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2025 22:36:05.7705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5cca780-9e50-4d1d-0f76-08ddfc83ea57 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6217 Content-Type: text/plain; charset="utf-8" The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not accessible to other subsystems. Change DVSEC name formatting to follow the existing PCI format in pci_regs.h. The current format uses CXL_DVSEC_XYZ. Change to be PCI_DVSEC_C= XL_XYZ. Reuse the existing formatting. Update existing occurrences to match the name change. Update the inline documentation to refer to latest CXL spec version. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang ---- Changes in v11 -> v12: - Change formatting to be same as existing definitions - Change GENMASK() -> __GENMASK() and BIT() to _BITUL() Changes in v10 -> v11: - New commit --- drivers/cxl/core/pci.c | 62 +++++++++++++++++----------------- drivers/cxl/core/regs.c | 12 +++---- drivers/cxl/cxlpci.h | 53 ----------------------------- drivers/cxl/pci.c | 2 +- drivers/pci/pci.c | 18 +++++----- include/uapi/linux/pci_regs.h | 63 ++++++++++++++++++++++++++++++++--- 6 files changed, 107 insertions(+), 103 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a009a51cb0de..a74a39bd909c 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -157,19 +157,19 @@ static int cxl_dvsec_mem_range_valid(struct cxl_dev_s= tate *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM INFO VALID bit first, give up after 1s */ i =3D 1; do { rc =3D pci_read_config_dword(pdev, - d + CXL_DVSEC_RANGE_SIZE_LOW(id), + d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - valid =3D FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp); + valid =3D FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp); if (valid) break; msleep(1000); @@ -193,17 +193,17 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_= state *cxlds, int id) int rc, i; u32 temp; =20 - if (id > CXL_DVSEC_RANGE_MAX) + if (id > PCI_DVSEC_CXL_RANGE_MAX) return -EINVAL; =20 /* Check MEM ACTIVE bit, up to 60s timeout by default */ for (i =3D media_ready_timeout; i; i--) { rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - active =3D FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp); + active =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp); if (active) break; msleep(1000); @@ -232,11 +232,11 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) u16 cap; =20 rc =3D pci_read_config_word(pdev, - d + CXL_DVSEC_CAP_OFFSET, &cap); + d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); for (i =3D 0; i < hdm_count; i++) { rc =3D cxl_dvsec_mem_range_valid(cxlds, i); if (rc) @@ -264,16 +264,16 @@ static int cxl_set_mem_enable(struct cxl_dev_state *c= xlds, u16 val) u16 ctrl; int rc; =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc < 0) return rc; =20 - if ((ctrl & CXL_DVSEC_MEM_ENABLE) =3D=3D val) + if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) =3D=3D val) return 1; - ctrl &=3D ~CXL_DVSEC_MEM_ENABLE; + ctrl &=3D ~PCI_DVSEC_CXL_MEM_ENABLE; ctrl |=3D val; =20 - rc =3D pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl); + rc =3D pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, ctrl); if (rc < 0) return rc; =20 @@ -289,7 +289,7 @@ static int devm_cxl_enable_mem(struct device *host, str= uct cxl_dev_state *cxlds) { int rc; =20 - rc =3D cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE); + rc =3D cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE); if (rc < 0) return rc; if (rc > 0) @@ -351,11 +351,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return -ENXIO; } =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP_OFFSET, &cap); if (rc) return rc; =20 - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) { dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; } @@ -366,7 +366,7 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * driver is for a spec defined class code which must be CXL.mem * capable, there is no point in continuing to enable CXL.mem. */ - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT_MASK, cap); if (!hdm_count || hdm_count > 2) return -EINVAL; =20 @@ -375,11 +375,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * disabled, and they will remain moot after the HDM Decoder * capability is enabled. */ - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL_OFFSET, &ctrl); if (rc) return rc; =20 - info->mem_enabled =3D FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); + info->mem_enabled =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl); if (!info->mem_enabled) return 0; =20 @@ -392,35 +392,35 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return rc; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp); if (rc) return rc; =20 size =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp); if (rc) return rc; =20 - size |=3D temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; + size |=3D temp & PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK; if (!size) { continue; } =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp); if (rc) return rc; =20 base =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp); if (rc) return rc; =20 - base |=3D temp & CXL_DVSEC_MEM_BASE_LOW_MASK; + base |=3D temp & PCI_DVSEC_CXL_MEM_BASE_LOW_MASK; =20 info->dvsec_range[ranges++] =3D (struct range) { .start =3D base, @@ -828,7 +828,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev) is_port =3D false; =20 dvsec =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF); + is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF); if (!dvsec) dev_warn(dev, "%s GPF DVSEC not present\n", is_port ? "Port" : "Device"); @@ -844,14 +844,14 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev= , int dvsec, int phase) =20 switch (phase) { case 1: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK; break; case 2: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK; break; default: return -EINVAL; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..fb70ffbba72d 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -271,10 +271,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, "CXL"); static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_= hi, struct cxl_register_map *map) { - u8 reg_type =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); - int bar =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo); + u8 reg_type =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK, reg_lo= ); + int bar =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK, reg_lo); u64 offset =3D ((u64)reg_hi << 32) | - (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK); + (reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK); =20 if (offset > pci_resource_len(pdev, bar)) { dev_warn(&pdev->dev, @@ -311,15 +311,15 @@ static int __cxl_find_regblock_instance(struct pci_de= v *pdev, enum cxl_regloc_ty }; =20 regloc =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - CXL_DVSEC_REG_LOCATOR); + PCI_DVSEC_CXL_REG_LOCATOR); if (!regloc) return -ENXIO; =20 pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); regloc_size =3D FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); =20 - regloc +=3D CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET; - regblocks =3D (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; + regloc +=3D PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET; + regblocks =3D (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET) / 8; =20 for (i =3D 0; i < regblocks; i++, regloc +=3D 8) { u32 reg_lo, reg_hi; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 970e84cf49e9..0c8b6ee7b6de 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -7,59 +7,6 @@ =20 #define CXL_MEMORY_PROGIF 0x10 =20 -/* - * See section 8.1 Configuration Space Registers in the CXL 2.0 - * Specification. Names are taken straight from the specification with "CX= L" and - * "DVSEC" redundancies removed. When obvious, abbreviations may be used. - */ -#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) - -/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ -#define CXL_DVSEC_PCIE_DEVICE 0 -#define CXL_DVSEC_CAP_OFFSET 0xA -#define CXL_DVSEC_MEM_CAPABLE BIT(2) -#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) -#define CXL_DVSEC_CTRL_OFFSET 0xC -#define CXL_DVSEC_MEM_ENABLE BIT(2) -#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) -#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) -#define CXL_DVSEC_MEM_INFO_VALID BIT(0) -#define CXL_DVSEC_MEM_ACTIVE BIT(1) -#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28) -#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) -#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) -#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) - -#define CXL_DVSEC_RANGE_MAX 2 - -/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ -#define CXL_DVSEC_FUNCTION_MAP 2 - -/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ -#define CXL_DVSEC_PORT_EXTENSIONS 3 - -/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ -#define CXL_DVSEC_PORT_GPF 4 -#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8) -#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8) - -/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ -#define CXL_DVSEC_DEVICE_GPF 5 - -/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ -#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 - -/* CXL 2.0 8.1.9: Register Locator DVSEC */ -#define CXL_DVSEC_REG_LOCATOR 8 -#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC -#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) - /* * NOTE: Currently all the functions which are enabled for CXL require the= ir * vectors to be in the first 16. Use this as the default max. diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd100ac31672..bd95be1f3d5c 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -933,7 +933,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) cxlds->rcd =3D is_cxl_restricted(pdev); cxlds->serial =3D pci_get_dsn(pdev); cxlds->cxl_dvsec =3D pci_find_dvsec_capability( - pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE); if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n"); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b0f4d98036cd..1a4f61caa0db 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5041,7 +5041,7 @@ static int pci_dev_reset_slot_function(struct pci_dev= *dev, bool probe) static u16 cxl_port_dvsec(struct pci_dev *dev) { return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, - PCI_DVSEC_CXL_PORT); + PCI_DVSEC_CXL_PORT_EXT); } =20 static bool cxl_sbr_masked(struct pci_dev *dev) @@ -5053,7 +5053,9 @@ static bool cxl_sbr_masked(struct pci_dev *dev) if (!dvsec) return false; =20 - rc =3D pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); + rc =3D pci_read_config_word(dev, + dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, + ®); if (rc || PCI_POSSIBLE_ERROR(reg)) return false; =20 @@ -5062,7 +5064,7 @@ static bool cxl_sbr_masked(struct pci_dev *dev) * bit in Bridge Control has no effect. When 1, the Port generates * hot reset when the SBR bit is set to 1. */ - if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) + if (reg & PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR) return false; =20 return true; @@ -5107,22 +5109,22 @@ static int cxl_reset_bus_function(struct pci_dev *d= ev, bool probe) if (probe) return 0; =20 - rc =3D pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); + rc =3D pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OF= FSET, ®); if (rc) return -ENOTTY; =20 - if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { + if (reg & PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR) { val =3D reg; } else { - val =3D reg | PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR; - pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, + val =3D reg | PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR; + pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, val); } =20 rc =3D pci_reset_bus_function(dev, probe); =20 if (reg !=3D val) - pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, + pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET, reg); =20 return rc; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f5b17745de60..bd03799612d3 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1234,9 +1234,64 @@ /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE = */ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_= RSP_3_TYPE =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ -#define PCI_DVSEC_CXL_PORT 3 -#define PCI_DVSEC_CXL_PORT_CTL 0x0c -#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +/* Compute Express Link (CXL r3.2, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ + +#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20) + +/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE 0 +#define PCI_DVSEC_CXL_CAP_OFFSET 0xA +#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2) +#define PCI_DVSEC_CXL_HDM_COUNT_MASK __GENMASK(5, 4) +#define PCI_DVSEC_CXL_CTRL_OFFSET 0xC +#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2) +#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0) +#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1) +#define PCI_DVSEC_CXL_MEM_SIZE_LOW_MASK __GENMASK(31, 28) +#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_BASE_LOW_MASK __GENMASK(31, 28) + +#define PCI_DVSEC_CXL_RANGE_MAX 2 + +/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */ +#define PCI_DVSEC_CXL_FUNCTION_MAP 2 + +/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */ +#define PCI_DVSEC_CXL_PORT_EXT 3 +#define PCI_DVSEC_CXL_PORT_EXT_CTL_OFFSET 0x0c +#define PCI_DVSEC_CXL_PORT_EXT_CTL_UNMASK_SBR 0x00000001 + +/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */ +#define PCI_DVSEC_CXL_PORT_GPF 4 +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8) + +/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE_GPF 5 + +/* CXL 3.2 8.1.8: PCIe DVSEC for Flex Bus Port */ +#define PCI_DVSEC_CXL_FLEXBUS_PORT 7 +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET 0xE +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK _BITUL(0) +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK _BITUL(2) + +/* CXL 3.2 8.1.9: Register Locator DVSEC */ +#define PCI_DVSEC_CXL_REG_LOCATOR 8 +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1_OFFSET 0xC +#define PCI_DVSEC_CXL_REG_LOCATOR_BIR_MASK __GENMASK(2, 0) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16) =20 #endif /* LINUX_PCI_REGS_H */ --=20 2.34.1