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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.9 via Frontend Transport; Thu, 25 Sep 2025 22:39:13 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 25 Sep 2025 15:39:11 -0700 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v12 24/25] CXL/PCI: Enable CXL protocol errors during CXL Port probe Date: Thu, 25 Sep 2025 17:34:39 -0500 Message-ID: <20250925223440.3539069-25-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925223440.3539069-1-terry.bowman@amd.com> References: <20250925223440.3539069-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|MN2PR12MB4288:EE_ X-MS-Office365-Filtering-Correlation-Id: e6e9b114-64b1-419c-71bf-08ddfc845a0a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2025 22:39:13.2123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6e9b114-64b1-419c-71bf-08ddfc845a0a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4288 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang --- Changes in v11->v12: - None Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/ras.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 45f92defca64..ea65001daba1 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -238,6 +238,21 @@ static inline void cxl_disable_rch_root_ints(struct cx= l_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } #endif =20 +static void cxl_unmask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -391,7 +406,10 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) =20 cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); + return; } + + cxl_unmask_proto_interrupts(dport->dport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 @@ -402,8 +420,12 @@ static void cxl_uport_init_ras_reporting(struct cxl_po= rt *port, =20 map->host =3D host; if (cxl_map_component_regs(map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + cxl_unmask_proto_interrupts(port->uport_dev); } =20 void cxl_switch_port_init_ras(struct cxl_port *port) @@ -440,6 +462,8 @@ void cxl_endpoint_port_init_ras(struct cxl_port *ep) } =20 cxl_dport_init_ras_reporting(parent_dport, cxlmd->cxlds->dev); + + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); =20 --=20 2.34.1