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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.9 via Frontend Transport; Thu, 25 Sep 2025 22:39:01 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 25 Sep 2025 15:39:00 -0700 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v12 23/25] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Date: Thu, 25 Sep 2025 17:34:38 -0500 Message-ID: <20250925223440.3539069-24-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925223440.3539069-1-terry.bowman@amd.com> References: <20250925223440.3539069-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|DM4PR12MB6662:EE_ X-MS-Office365-Filtering-Correlation-Id: 04ae7286-7e4c-4a46-6dcd-08ddfc84533c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2025 22:39:01.7952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04ae7286-7e4c-4a46-6dcd-08ddfc84533c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6662 Content-Type: text/plain; charset="utf-8" Populate the cxl_do_recovery() function with uncorrectable protocol error (= UCE) handling. Follow similar design as found in PCIe error driver, pcie_do_recovery(). One difference is cxl_do_recovery() will treat all UCEs as fatal with a kernel panic. This is to prevent corruption on CXL memory. Introduce cxl_walk_port(). Make this analogous to pci_walk_bridge() but wal= king CXL ports instead. This will iterate through the CXL topology from the erroring device through the downstream CXL Ports and Endpoints. Export pci_aer_clear_fatal_status() for CXL to use if a UCE is not found. Signed-off-by: Terry Bowman --- Changes in v11->v12: - Cleaned up port discovery in cxl_do_recovery() (Dave) - Added PCI_EXP_TYPE_RC_END to type check in cxl_report_error_detected() Changes in v10->v11: - pci_ers_merge_results() - Move to earlier patch --- drivers/cxl/core/ras.c | 111 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 7e8d63c32d72..45f92defca64 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -443,8 +443,119 @@ void cxl_endpoint_port_init_ras(struct cxl_port *ep) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); =20 +static int cxl_report_error_detected(struct device *dev, void *data) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + pci_ers_result_t vote, *result =3D data; + + guard(device)(dev); + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_RC_END)) { + if (!cxl_pci_drv_bound(pdev)) + return 0; + + vote =3D cxl_error_detected(dev); + } else { + vote =3D cxl_port_error_detected(dev); + } + + *result =3D pci_ers_merge_result(*result, vote); + + return 0; +} + +static int match_port_by_parent_dport(struct device *dev, const void *dpor= t_dev) +{ + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->parent_dport->dport_dev =3D=3D dport_dev; +} + +static void cxl_walk_port(struct device *port_dev, + int (*cb)(struct device *, void *), + void *userdata) +{ + struct cxl_dport *dport =3D NULL; + struct cxl_port *port; + unsigned long index; + + if (!port_dev) + return; + + port =3D to_cxl_port(port_dev); + if (port->uport_dev && dev_is_pci(port->uport_dev)) + cb(port->uport_dev, userdata); + + xa_for_each(&port->dports, index, dport) + { + struct device *child_port_dev __free(put_device) =3D + bus_find_device(&cxl_bus_type, &port->dev, dport->dport_dev, + match_port_by_parent_dport); + + cb(dport->dport_dev, userdata); + + cxl_walk_port(child_port_dev, cxl_report_error_detected, userdata); + } + + if (is_cxl_endpoint(port)) + cb(port->uport_dev->parent, userdata); +} + static void cxl_do_recovery(struct device *dev) { + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port =3D NULL; + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) { + struct cxl_dport *dport; + struct cxl_port *rp_port __free(put_cxl_port) =3D find_cxl_port(&pdev->d= ev, &dport); + + port =3D rp_port; + + } else if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_UPSTREAM) { + struct cxl_port *us_port __free(put_cxl_port) =3D find_cxl_port_by_uport= (&pdev->dev); + + port =3D us_port; + + } else if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_RC_END)) { + struct cxl_dev_state *cxlds; + + if (!cxl_pci_drv_bound(pdev)) + return; + + cxlds =3D pci_get_drvdata(pdev); + port =3D cxlds->cxlmd->endpoint; + } + + if (!port) { + dev_err(dev, "Failed to find the CXL device\n"); + return; + } + + cxl_walk_port(&port->dev, cxl_report_error_detected, &status); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (cxl_error_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } } =20 static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iome= m *ras_base) --=20 2.34.1