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Thu, 25 Sep 2025 22:38:17 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 25 Sep 2025 15:38:16 -0700 From: Terry Bowman To: , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v12 19/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Date: Thu, 25 Sep 2025 17:34:34 -0500 Message-ID: <20250925223440.3539069-20-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925223440.3539069-1-terry.bowman@amd.com> References: <20250925223440.3539069-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|DS4PR12MB9771:EE_ X-MS-Office365-Filtering-Correlation-Id: cdb78bba-5628-4df4-f2ff-08ddfc8438f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2025 22:38:17.7109 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdb78bba-5628-4df4-f2ff-08ddfc8438f5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9771 Content-Type: text/plain; charset="utf-8" CXL devices handle protocol errors via driver-specific callbacks rather than the generic pci_driver::err_handlers by default. The callbacks are implemented in the cxl_pci driver and are not part of struct pci_driver, so cxl_core must verify that a device is actually bound to the cxl_pci module's driver before invoking the callbacks (the device could be bound to another driver, e.g. VFIO). However, cxl_core can not reference symbols in the cxl_pci module because it creates a circular dependency. This prevents cxl_core from checking the EP's bound driver and calling the callbacks. To fix this, move drivers/cxl/pci.c into drivers/cxl/core/pci_drv.c and build it as part of the cxl_core module. Compile into cxl_core using CXL_PCI and CXL_CORE Kconfig dependencies. This removes the standalone cxl_= pci module, consolidates the cxl_pci driver code into cxl_core, and eliminates the circular dependency so cxl_core can safely perform bound-driver checks and invoke the CXL PCI callbacks. Introduce cxl_pci_drv_bound() to return boolean depending on if the PCI EP parameter is bound to a CXL driver instance. This will be used in future patch when dequeuing work from the kfifo. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- Changes in v11 -> v12: - New patch --- drivers/cxl/Kconfig | 6 +++--- drivers/cxl/Makefile | 2 -- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 9 +++++++++ drivers/cxl/{pci.c =3D> core/pci_drv.c} | 16 ++++++++-------- drivers/cxl/core/port.c | 3 +++ 6 files changed, 24 insertions(+), 13 deletions(-) rename drivers/cxl/{pci.c =3D> core/pci_drv.c} (99%) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 028201e24523..9ee76bae02d5 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -20,7 +20,7 @@ menuconfig CXL_BUS if CXL_BUS =20 config CXL_PCI - tristate "PCI manageability" + bool "PCI manageability" default CXL_BUS help The CXL specification defines a "CXL memory device" sub-class in the @@ -29,12 +29,12 @@ config CXL_PCI memory to be mapped into the system address map (Host-managed Device Memory (HDM)). =20 - Say 'y/m' to enable a driver that will attach to CXL memory expander + Say 'y' to enable a driver that will attach to CXL memory expander devices enumerated by the memory device class code for configuration and management primarily via the mailbox interface. See Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more details. =20 - If unsure say 'm'. + If unsure say 'y'. =20 config CXL_MEM_RAW_COMMANDS bool "RAW Command Interface for Memory Devices" diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 2caa90fa4bf2..ff6add88b6ae 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -12,10 +12,8 @@ obj-$(CONFIG_CXL_PORT) +=3D cxl_port.o obj-$(CONFIG_CXL_ACPI) +=3D cxl_acpi.o obj-$(CONFIG_CXL_PMEM) +=3D cxl_pmem.o obj-$(CONFIG_CXL_MEM) +=3D cxl_mem.o -obj-$(CONFIG_CXL_PCI) +=3D cxl_pci.o =20 cxl_port-y :=3D port.o cxl_acpi-y :=3D acpi.o cxl_pmem-y :=3D pmem.o security.o cxl_mem-y :=3D mem.o -cxl_pci-y :=3D pci.o diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index b2930cc54f8b..91f43c3f2292 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -20,3 +20,4 @@ cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o +cxl_core-$(CONFIG_CXL_PCI) +=3D pci_drv.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 74c64d458f12..9ceff8acf844 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -202,4 +202,13 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, cons= t uuid_t *feat_uuid, u16 *return_code); #endif =20 +#ifdef CONFIG_CXL_PCI +bool cxl_pci_drv_bound(struct pci_dev *pdev); +int cxl_pci_driver_init(void); +void cxl_pci_driver_exit(void); +#else +static inline bool cxl_pci_drv_bound(struct pci_dev *pdev) { return false;= }; +static inline int cxl_pci_driver_init(void) { return 0; } +static inline void cxl_pci_driver_exit(void) { } +#endif #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/core/pci_drv.c similarity index 99% rename from drivers/cxl/pci.c rename to drivers/cxl/core/pci_drv.c index 71fb8709081e..746b5017d336 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/core/pci_drv.c @@ -1132,6 +1132,12 @@ static struct pci_driver cxl_pci_driver =3D { }, }; =20 +bool cxl_pci_drv_bound(struct pci_dev *pdev) +{ + return (pdev->driver =3D=3D &cxl_pci_driver); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_drv_bound, "CXL"); + #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_handle_cper_event(enum cxl_event_type ev_type, struct cxl_cper_event_rec *rec) @@ -1178,7 +1184,7 @@ static void cxl_cper_work_fn(struct work_struct *work) } static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); =20 -static int __init cxl_pci_driver_init(void) +int __init cxl_pci_driver_init(void) { int rc; =20 @@ -1193,15 +1199,9 @@ static int __init cxl_pci_driver_init(void) return rc; } =20 -static void __exit cxl_pci_driver_exit(void) +void cxl_pci_driver_exit(void) { cxl_cper_unregister_work(&cxl_cper_work); cancel_work_sync(&cxl_cper_work); pci_unregister_driver(&cxl_pci_driver); } - -module_init(cxl_pci_driver_init); -module_exit(cxl_pci_driver_exit); -MODULE_DESCRIPTION("CXL: PCI manageability"); -MODULE_LICENSE("GPL v2"); -MODULE_IMPORT_NS("CXL"); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index bd4be046888a..56fa4ac33e8b 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2502,6 +2502,8 @@ static __init int cxl_core_init(void) if (rc) goto err_ras; =20 + cxl_pci_driver_init(); + return 0; =20 err_ras: @@ -2517,6 +2519,7 @@ static __init int cxl_core_init(void) =20 static void cxl_core_exit(void) { + cxl_pci_driver_exit(); cxl_ras_exit(); cxl_region_exit(); bus_unregister(&cxl_bus_type); --=20 2.34.1