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Thu, 25 Sep 2025 13:06:31 -0700 (PDT) From: Tomer Maimon To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH v3 1/3] arm64: dts: nuvoton: fix warning and nodes order Date: Thu, 25 Sep 2025 23:06:23 +0300 Message-Id: <20250925200625.573902-2-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925200625.573902-1-tmaimon77@gmail.com> References: <20250925200625.573902-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix the warning in the gcr and timer nodes, and modify nodes order by ascending unit address. Signed-off-by: Tomer Maimon --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 35 +++++++++---------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 24133528b8e9..a43514f624c0 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -18,7 +18,7 @@ soc { ranges; =20 gcr: system-controller@f0800000 { - compatible =3D "nuvoton,npcm845-gcr", "syscon"; + compatible =3D "nuvoton,npcm845-gcr", "syscon", "simple-mfd"; reg =3D <0x0 0xf0800000 0x0 0x1000>; }; =20 @@ -59,23 +59,6 @@ apb { ranges =3D <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; =20 - peci: peci-controller@100000 { - compatible =3D "nuvoton,npcm845-peci"; - reg =3D <0x100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk NPCM8XX_CLK_APB3>; - cmd-timeout-ms =3D <1000>; - status =3D "disabled"; - }; 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Thu, 25 Sep 2025 13:06:34 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e34074983sm43901835e9.10.2025.09.25.13.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Sep 2025 13:06:33 -0700 (PDT) From: Tomer Maimon To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH v3 2/3] arm64: dts: nuvoton: npcm845: Add peripheral nodes Date: Thu, 25 Sep 2025 23:06:24 +0300 Message-Id: <20250925200625.573902-3-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925200625.573902-1-tmaimon77@gmail.com> References: <20250925200625.573902-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services. Signed-off-by: Tomer Maimon --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 697 +++++++++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 7 + 2 files changed, 703 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index a43514f624c0..485705c68e04 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -35,6 +36,11 @@ gic: interrupt-controller@dfff9000 { }; }; =20 + udc0_phy: usb-phy { + compatible =3D "usb-nop-xceiv"; + #phy-cells =3D <0>; + }; + ahb { #address-cells =3D <2>; #size-cells =3D <2>; @@ -51,7 +57,260 @@ clk: rstc: reset-controller@f0801000 { #clock-cells =3D <1>; }; =20 - apb { + gmac1: ethernet@f0804000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0804000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rg2_pins + &rg2mdio_pins>; + status =3D "disabled"; + }; + + gmac2: ethernet@f0806000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0806000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r1_pins + &r1err_pins + &r1md_pins>; + status =3D "disabled"; + }; + + gmac3: ethernet@f0808000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0808000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r2_pins + &r2err_pins + &r2md_pins>; + status =3D "disabled"; + }; + + mc: memory-controller@f0824000 { + compatible =3D "nuvoton,npcm845-memory-controller"; + reg =3D <0x0 0xf0824000 0x0 0x1000>; + interrupts =3D ; + }; + + udc0: usb@f0830000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0830000 0x0 0x1000 + 0x0 0xfffeb000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc1: usb@f0831000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0831000 0x0 0x1000 + 0x0 0xfffeb800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc2: usb@f0832000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0832000 0x0 0x1000 + 0x0 0xfffec000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc3: usb@f0833000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0833000 0x0 0x1000 + 0x0 0xfffec800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc4: usb@f0834000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0834000 0x0 0x1000 + 0x0 0xfffed000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc5: usb@f0835000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0835000 0x0 0x1000 + 0x0 0xfffed800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc6: usb@f0836000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0836000 0x0 0x1000 + 0x0 0xfffee000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc7: usb@f0837000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0837000 0x0 0x1000 + 0x0 0xfffee800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc8: usb@f0838000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0838000 0x0 0x1000 + 0x0 0xfffef000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + nuvoton,sysgcr =3D <&gcr 0x9C 0xC000 0xC000>; + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc9: usb@f0839000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0839000 0x0 0x1000 + 0x0 0xfffef800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + nuvoton,sysgcr =3D <&gcr 0x9C 0x3000 0x3000>; + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + sdhci: mmc@f0842000 { + compatible =3D "nuvoton,npcm845-sdhci"; + reg =3D <0x0 0xf0842000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc8_pins + &mmc_pins>; + status =3D "disabled"; + }; + + fiu0: spi@fb000000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb000000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI0>; + clock-names =3D "clk_ahb"; + status =3D "disabled"; + }; + + fiu1: spi@fb002000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb002000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI1>; + clock-names =3D "clk_spi1"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + status =3D "disabled"; + }; + + fiu3: spi@c0000000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xc0000000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI3>; + clock-names =3D "clk_spi3"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi3_pins>; + status =3D "disabled"; + }; + + fiux: spi@fb001000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xf8000000 0x0 0x2000000>; + reg-names =3D "control", "memory"; + clocks =3D <&clk NPCM8XX_CLK_SPIX>; + clock-names =3D "clk_ahb"; + status =3D "disabled"; + }; + + + apb: bus@f0000000 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "simple-bus"; @@ -164,6 +423,442 @@ peci: peci-controller@100000 { cmd-timeout-ms =3D <1000>; status =3D "disabled"; }; + + rng: rng@b000 { + compatible =3D "nuvoton,npcm845-rng"; + reg =3D <0xb000 0x8>; + status =3D "disabled"; + }; + + adc: adc@c000 { + compatible =3D "nuvoton,npcm845-adc"; + reg =3D <0xC000 0x8>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_ADC>; + resets =3D <&rstc 0x20 27>; + status =3D "disabled"; + }; + + i2c0: i2c@80000 { + reg =3D <0x80000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb0_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c1: i2c@81000 { + reg =3D <0x81000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb1_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c2: i2c@82000 { + reg =3D <0x82000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb2_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c3: i2c@83000 { + reg =3D <0x83000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb3_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c4: i2c@84000 { + reg =3D <0x84000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb4_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c5: i2c@85000 { + reg =3D <0x85000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb5_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c6: i2c@86000 { + reg =3D <0x86000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb6_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c7: i2c@87000 { + reg =3D <0x87000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb7_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c8: i2c@88000 { + reg =3D <0x88000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb8_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c9: i2c@89000 { + reg =3D <0x89000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb9_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c10: i2c@8a000 { + reg =3D <0x8a000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb10_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c11: i2c@8b000 { + reg =3D <0x8b000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb11_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c12: i2c@8c000 { + reg =3D <0x8c000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb12_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c13: i2c@8d000 { + reg =3D <0x8d000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb13_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c14: i2c@8e000 { + reg =3D <0x8e000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb14_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c15: i2c@8f000 { + reg =3D <0x8f000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb15_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c16: i2c@fff00000 { + reg =3D <0xfff00000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb16_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c17: i2c@fff01000 { + reg =3D <0xfff01000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb17_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c18: i2c@fff02000 { + reg =3D <0xfff02000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb18_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c19: i2c@fff03000 { + reg =3D <0xfff03000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb19_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c20: i2c@fff04000 { + reg =3D <0xfff04000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb20_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c21: i2c@fff05000 { + reg =3D <0xfff05000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb21_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c22: i2c@fff06000 { + reg =3D <0xfff06000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb22_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c23: i2c@fff07000 { + reg =3D <0xfff07000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb23_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c24: i2c@fff08000 { + reg =3D <0xfff08000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c25: i2c@fff09000 { + reg =3D <0xfff09000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c26: i2c@fff0a000 { + reg =3D <0xfff0a000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + pwm_fan:pwm-fan-controller@103000 { + compatible =3D "nuvoton,npcm845-pwm-fan"; + reg =3D <0x103000 0x3000>, + <0x180000 0x8000>; + reg-names =3D "pwm", "fan"; + clocks =3D <&clk NPCM8XX_CLK_APB3>, + <&clk NPCM8XX_CLK_APB4>; + clock-names =3D "pwm","fan"; + interrupts =3D , + , + , + , + , + , + , + ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &pwm8_pins &pwm9_pins + &pwm10_pins &pwm11_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status =3D "disabled"; + }; + + pspi: spi@201000 { + compatible =3D "nuvoton,npcm845-pspi"; + reg =3D <0x201000 0x1000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pspi_pins>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_APB5>; + clock-names =3D "clk_apb5"; + resets =3D <&rstc 0x24 23>; + status =3D "disabled"; + }; + }; }; =20 diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/= boot/dts/nuvoton/nuvoton-npcm845.dtsi index 383938dcd3ce..21dea323612d 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -75,4 +75,11 @@ timer { , ; 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Thu, 25 Sep 2025 13:06:35 -0700 (PDT) From: Tomer Maimon To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH v3 3/3] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes Date: Thu, 25 Sep 2025 23:06:25 +0300 Message-Id: <20250925200625.573902-4-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250925200625.573902-1-tmaimon77@gmail.com> References: <20250925200625.573902-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access. Signed-off-by: Tomer Maimon --- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 440 ++++++++++++++++++ 1 file changed, 440 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm= 64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 2638ee1c3846..53e6a0af5a21 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -9,6 +9,42 @@ / { compatible =3D "nuvoton,npcm845-evb", "nuvoton,npcm845"; =20 aliases { + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + ethernet3 =3D &gmac3; + fiu0 =3D &fiu0; + fiu1 =3D &fiu3; + fiu2 =3D &fiux; + fiu3 =3D &fiu1; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + i2c11 =3D &i2c11; + i2c12 =3D &i2c12; + i2c13 =3D &i2c13; + i2c14 =3D &i2c14; + i2c15 =3D &i2c15; + i2c16 =3D &i2c16; + i2c17 =3D &i2c17; + i2c18 =3D &i2c18; + i2c19 =3D &i2c19; + i2c20 =3D &i2c20; + i2c21 =3D &i2c21; + i2c22 =3D &i2c22; + i2c23 =3D &i2c23; + i2c24 =3D &i2c24; + i2c25 =3D &i2c25; + i2c26 =3D &i2c26; + mdio-gpio0 =3D &mdio0; + mdio-gpio1 =3D &mdio1; serial0 =3D &serial0; }; =20 @@ -16,7 +52,32 @@ chosen { stdout-path =3D &serial0; }; =20 + mdio0: mdio-0 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + gpios =3D <&gpio1 25 GPIO_ACTIVE_HIGH>, + <&gpio1 26 GPIO_ACTIVE_HIGH>; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + + mdio1: mdio-1 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + gpios =3D <&gpio2 27 GPIO_ACTIVE_HIGH>, + <&gpio2 28 GPIO_ACTIVE_HIGH>; + + phy1: ethernet-phy@0 { + reg =3D <0>; + }; + }; + memory@0 { + device_type =3D "memory"; reg =3D <0x0 0x0 0x0 0x40000000>; }; =20 @@ -25,12 +86,391 @@ refclk: refclk-25mhz { clock-frequency =3D <25000000>; #clock-cells =3D <0>; }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tip_reserved: tip@0 { + reg =3D <0x0 0x0 0x0 0x6200000>; + }; + }; +}; + +&adc { + #io-channel-cells =3D <1>; + status =3D "okay"; +}; + +&fiu0 { + status =3D "okay"; + flash@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "bb-uboot-1"; + reg =3D <0x0000000 0x80000>; + read-only; + }; + partition@80000 { + label =3D "bb-uboot-2"; + reg =3D <0x0080000 0x80000>; + read-only; + }; + partition@100000 { + label =3D "env-param"; + reg =3D <0x0100000 0x40000>; + read-only; + }; + partition@140000 { + label =3D "spare"; + reg =3D <0x0140000 0xC0000>; + }; + partition@200000 { + label =3D "kernel"; + reg =3D <0x0200000 0x400000>; + }; + partition@600000 { + label =3D "rootfs"; + reg =3D <0x0600000 0x700000>; + }; + partition@d00000 { + label =3D "spare1"; + reg =3D <0x0d00000 0x200000>; + }; + partition@f00000 { + label =3D "spare2"; + reg =3D <0x0f00000 0x200000>; + }; + partition@1100000 { + label =3D "spare3"; + reg =3D <0x1100000 0x200000>; + }; + partition@1300000 { + label =3D "spare4"; + reg =3D <0x1300000 0x0>; + }; + }; + }; +}; + +&fiu1 { + status =3D "okay"; + flash@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "spi1-system1"; + reg =3D <0x0 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 =3D <&spi3_pins>, <&spi3quad_pins>; + status =3D "okay"; + flash@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "spi3-system1"; + reg =3D <0x0 0x0>; + }; + }; + }; +}; + +&fiux { + spix-mode; +}; + +&gmac1 { + phy-mode =3D "rgmii-id"; + snps,eee-force-disable; + status =3D "okay"; +}; + +&gmac2 { + phy-mode =3D "rmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r1_pins + &r1oen_pins>; + phy-handle =3D <&phy0>; + status =3D "okay"; +}; + +&gmac3 { + phy-mode =3D "rmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r2_pins + &r2oen_pins>; + phy-handle =3D <&phy1>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +&i2c2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ipmb@10 { + compatible =3D "ipmb-dev"; + reg =3D <0x10>; + i2c-protocol; + }; +}; + +&i2c3 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ipmb@11 { + compatible =3D "ipmb-dev"; + reg =3D <0x11>; + i2c-protocol; + }; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + tmp100@48 { + compatible =3D "tmp100"; + reg =3D <0x48>; + status =3D "okay"; + }; +}; + +&i2c7 { + status =3D "okay"; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; +}; + +&i2c10 { + status =3D "okay"; +}; + +&i2c11 { + status =3D "okay"; +}; + +&i2c12 { + status =3D "okay"; +}; + +&i2c13 { + status =3D "okay"; +}; + +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&i2c16 { + status =3D "okay"; +}; + +&i2c17 { + status =3D "okay"; +}; + +&i2c18 { + status =3D "okay"; +}; + +&i2c19 { + status =3D "okay"; +}; + +&i2c20 { + status =3D "okay"; +}; + +&i2c21 { + status =3D "okay"; +}; + +&i2c22 { + status =3D "okay"; +}; + +&i2c23 { + status =3D "okay"; +}; + +&i2c24 { + status =3D "okay"; +}; + +&i2c25 { + status =3D "okay"; +}; + +&i2c26 { + status =3D "okay"; +}; + +&mc { + status =3D "okay"; +}; + +&peci { + status =3D "okay"; +}; + +&pwm_fan { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins>; + #address-cells =3D <1>; + #size-cells =3D <0>; + fan@0 { + reg =3D <0x00>; + fan-tach-ch =3D <0x0 0x1>; + cooling-levels =3D <127 255>; + }; + fan@1 { + reg =3D <0x01>; + fan-tach-ch =3D <0x2 0x3>; + cooling-levels =3D <127 255>; + }; + fan@2 { + reg =3D <0x02>; + fan-tach-ch =3D <0x4 0x5>; + cooling-levels =3D <127 255>; + }; + fan@3 { + reg =3D <0x03>; + fan-tach-ch =3D <0x6 0x7>; + cooling-levels =3D <127 255>; + }; + fan@4 { + reg =3D <0x04>; + fan-tach-ch =3D <0x8 0x9>; + cooling-levels =3D <127 255>; + }; + fan@5 { + reg =3D <0x05>; + fan-tach-ch =3D <0xa 0xb>; + cooling-levels =3D <127 255>; + }; + fan@6 { + reg =3D <0x06>; + fan-tach-ch =3D <0xc 0xd>; + cooling-levels =3D <127 255>; + }; + fan@7 { + reg =3D <0x07>; + fan-tach-ch =3D <0xe 0xf>; + cooling-levels =3D <127 255>; + }; +}; + +&rng { + status =3D "okay"; +}; + +&sdhci { + status =3D "okay"; }; =20 &serial0 { status =3D "okay"; }; =20 +&udc0 { + status =3D "okay"; +}; + +&udc1 { + status =3D "okay"; +}; + +&udc2 { + status =3D "okay"; +}; + +&udc3 { + status =3D "okay"; +}; + +&udc4 { + status =3D "okay"; +}; + +&udc5 { + status =3D "okay"; +}; + +&udc6 { + status =3D "okay"; +}; + +&udc7 { + status =3D "okay"; +}; + &watchdog1 { status =3D "okay"; }; --=20 2.34.1