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AJvYcCXx5z+Uv0DrX9f8kXT+ZeoUoJx/xKZ3EdxN1QvyDx0lGiP3P92m4AeqykrNkGK+gmldLOKX6/YE9IAqD34=@vger.kernel.org X-Gm-Message-State: AOJu0YwboP1dp2CHJcMhoZLWNoiNu6ChRZTRsJVof+erkqlvGZGN3bQ2 0ljFeklI42cMGCRlTcPxwNCEfc1z1/ok5onTuU27OlbLMhTFI6GHopIfyYcMWIHnu/7xgQJK7Af 6HENyF+4ZhQ== X-Google-Smtp-Source: AGHT+IHLZFcjDP1uOdSHMiRmqGh++GyPeC0pnmKnx0I1q+4QQqOyYsHBabeG4rCVjRJ5ZOi0XOjmMJDYy4wX X-Received: from ywblh8.prod.google.com ([2002:a05:690c:5608:b0:735:8634:be69]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:690c:4908:b0:739:ca5d:d97c with SMTP id 00721157ae682-763fa52a40dmr37249747b3.15.1758821275661; Thu, 25 Sep 2025 10:27:55 -0700 (PDT) Date: Thu, 25 Sep 2025 10:27:33 -0700 In-Reply-To: <20250925172736.960368-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250925172736.960368-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.536.g15c5d4f767-goog Message-ID: <20250925172736.960368-8-irogers@google.com> Subject: [PATCH v2 07/10] perf vendor events intel: Update meteorlake events to v1.17 From: Ian Rogers To: Thomas Falcon , Perry Taylor , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Caleb Biggers , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update lunarlake events to v1.17 released in: https://github.com/intel/perfmon/commit/ec387ac70602283d01da32c2ff5fe9cb15d= 3d25b Event json automatically generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/meteorlake/cache.json | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index aa0e2b0c4ba4..3a15a0f75b96 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core GenuineIntel-6-BD,v1.18,lunarlake,core -GenuineIntel-6-(AA|AC|B5),v1.16,meteorlake,core +GenuineIntel-6-(AA|AC|B5),v1.17,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-6-CC,v1.00,pantherlake,core diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/cache.json index f1d8db284a02..d4731e300d6d 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json @@ -1178,6 +1178,30 @@ "UMask": "0x3", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts writebacks of modified cachelines that= hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0008", + "PublicDescription": "Counts writebacks of modified cachelines tha= t hit in the L3 or were snooped from another core's caches. Available PDIST= counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts writebacks of non-modified cachelines = that hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.COREWB_NONM.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C1000", + "PublicDescription": "Counts writebacks of non-modified cachelines= that hit in the L3 or were snooped from another core's caches. Available P= DIST counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", "Counter": "0,1,2,3,4,5,6,7", @@ -1394,6 +1418,18 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts all data read, code read, RFO and ITOM= requests including demands and prefetches to the core caches (L1 or L2) th= at hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C4477", + "PublicDescription": "Counts all data read, code read, RFO and ITO= M requests including demands and prefetches to the core caches (L1 or L2) t= hat hit in the L3 or were snooped from another core's caches. Available PDI= ST counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Any memory transaction that reached the SQ.", "Counter": "0,1,2,3", --=20 2.51.0.536.g15c5d4f767-goog