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AJvYcCUvjvF6G9K4Qcap5bTZ2FHjekViq4Rd9KZpWJKPRTF8QvYnkXXUDnL01EhunE1oU9CxA8quxmZdlC+8In8=@vger.kernel.org X-Gm-Message-State: AOJu0Yx4sOhgG8QaAvzBBbIw7n2bTTVPwOSv6QUiCLWHbdbZ9KThZbhb 7Qr3MCym+0flfldSCseHYskO+c2dXd25dJFvUGzikPR4UmkKHr3/z5Olr63ieZQXRQPmz3iFuWx oFbWA9pUVDQ== X-Google-Smtp-Source: AGHT+IFFc5BlC0dIErbWqNCgrS2ViEIDDRdF30aQkF5/WJsq64pQCEH3ZIFKoU95QM7taLBtqRtw+GaCwjjV X-Received: from ybbgf10.prod.google.com ([2002:a05:6902:600a:b0:ea5:cc46:92d5]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a53:b043:0:b0:5ff:6c94:7f48 with SMTP id 956f58d0204a3-6361d4ea3aemr1960328d50.16.1758821263588; Thu, 25 Sep 2025 10:27:43 -0700 (PDT) Date: Thu, 25 Sep 2025 10:27:27 -0700 In-Reply-To: <20250925172736.960368-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250925172736.960368-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.536.g15c5d4f767-goog Message-ID: <20250925172736.960368-2-irogers@google.com> Subject: [PATCH v2 01/10] perf vendor events intel: Update alderlake events to v1.34 From: Ian Rogers To: Thomas Falcon , Perry Taylor , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Caleb Biggers , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update alderlake events to v1.34 released in: https://github.com/intel/perfmon/commit/80b773ebcf601b0e48e31f2184ffef933c4= d842e Event json automatically generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/alderlake/cache.json | 36 +++++++++++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/alderlake/cache.json index 6a56c9ad8e43..4cd535baf703 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json @@ -1062,6 +1062,30 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts writebacks of modified cachelines that= hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0008", + "PublicDescription": "Counts writebacks of modified cachelines tha= t hit in the L3 or were snooped from another core's caches. Available PDIST= counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts writebacks of non-modified cachelines = that hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.COREWB_NONM.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C1000", + "PublicDescription": "Counts writebacks of non-modified cachelines= that hit in the L3 or were snooped from another core's caches. Available P= DIST counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", "Counter": "0,1,2,3,4,5", @@ -1302,6 +1326,18 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts all data read, code read, RFO and ITOM= requests including demands and prefetches to the core caches (L1 or L2) th= at hit in the L3 or were snooped from another core's caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C4477", + "PublicDescription": "Counts all data read, code read, RFO and ITO= M requests including demands and prefetches to the core caches (L1 or L2) t= hat hit in the L3 or were snooped from another core's caches. Available PDI= ST counters: 0", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts L1 data cache software prefetches whic= h include T0/T1/T2 and NTA (except PREFETCHW) that have any type of respons= e.", "Counter": "0,1,2,3,4,5", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index d9daab4d8461..4b706599124d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.33,alderlake,core -GenuineIntel-6-BE,v1.33,alderlaken,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.34,alderlake,core +GenuineIntel-6-BE,v1.34,alderlaken,core GenuineIntel-6-C[56],v1.12,arrowlake,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v30,broadwell,core --=20 2.51.0.536.g15c5d4f767-goog