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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58313430496sm870084e87.27.2025.09.25.08.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Sep 2025 08:17:47 -0700 (PDT) From: Svyatoslav Ryhel To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Linus Walleij , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= , Dmitry Osipenko , Charan Pedumuru , Diogo Ivo , Aaron Kling , Arnd Bergmann Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v3 21/22] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Date: Thu, 25 Sep 2025 18:16:47 +0300 Message-ID: <20250925151648.79510-22-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250925151648.79510-1-clamor95@gmail.com> References: <20250925151648.79510-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CSI node to Tegra20 and Tegra30 device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 19 ++++++++++++++++++- arch/arm/boot/dts/nvidia/tegra30.dtsi | 24 ++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvid= ia/tegra20.dtsi index 6ae07b316c8a..5cdbf1246cf8 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ mpe@54040000 { =20 vi@54080000 { compatible =3D "nvidia,tegra20-vi"; - reg =3D <0x54080000 0x00040000>; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA20_CLK_VI>; resets =3D <&tegra_car 20>; @@ -72,6 +72,23 @@ vi@54080000 { power-domains =3D <&pd_venc>; operating-points-v2 =3D <&vi_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible =3D "nvidia,tegra20-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA20_CLK_CSI>; + power-domains =3D <&pd_venc>; + #nvidia,mipi-calibrate-cells =3D <1>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + }; }; =20 epp@540c0000 { diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvid= ia/tegra30.dtsi index 20b3248d4d2f..be752a245a55 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -150,8 +150,8 @@ mpe@54040000 { }; =20 vi@54080000 { - compatible =3D "nvidia,tegra30-vi"; - reg =3D <0x54080000 0x00040000>; + compatible =3D "nvidia,tegra30-vi", "nvidia,tegra20-vi"; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA30_CLK_VI>; resets =3D <&tegra_car 20>; @@ -162,6 +162,26 @@ vi@54080000 { iommus =3D <&mc TEGRA_SWGROUP_VI>; =20 status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible =3D "nvidia,tegra30-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names =3D "csi", "csia-pad", "csib-pad"; + power-domains =3D <&pd_venc>; + #nvidia,mipi-calibrate-cells =3D <1>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + }; }; =20 epp@540c0000 { --=20 2.48.1