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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58313430496sm870084e87.27.2025.09.25.08.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Sep 2025 08:17:37 -0700 (PDT) From: Svyatoslav Ryhel To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Linus Walleij , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= , Dmitry Osipenko , Charan Pedumuru , Diogo Ivo , Aaron Kling , Arnd Bergmann Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v3 15/22] staging: media: tegra-video: tegra20: simplify format align calculations Date: Thu, 25 Sep 2025 18:16:41 +0300 Message-ID: <20250925151648.79510-16-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250925151648.79510-1-clamor95@gmail.com> References: <20250925151648.79510-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify format align calculations by slightly modifying supported formats structure. Adjusted U and V offset calculations for planar formats since YUV420P bits per pixel is 12 (1 full plane for Y + 2 * 1/4 planes for U and V) so stride is width * 3/2, but offset must be calculated with plain width since each plain has stride width * 1. This aligns with downstream behavior which uses same approach for offset calculations. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 58 +++++++++------------ drivers/staging/media/tegra-video/vi.h | 3 +- 2 files changed, 27 insertions(+), 34 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 7c3ff843235d..b7a39723dfc2 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -280,20 +280,8 @@ static void tegra20_fmt_align(struct v4l2_pix_format *= pix, unsigned int bpp) pix->width =3D clamp(pix->width, TEGRA20_MIN_WIDTH, TEGRA20_MAX_WIDTH); pix->height =3D clamp(pix->height, TEGRA20_MIN_HEIGHT, TEGRA20_MAX_HEIGHT= ); =20 - switch (pix->pixelformat) { - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_VYUY: - case V4L2_PIX_FMT_YUYV: - case V4L2_PIX_FMT_YVYU: - pix->bytesperline =3D roundup(pix->width, 2) * 2; - pix->sizeimage =3D roundup(pix->width, 2) * 2 * pix->height; - break; - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YVU420: - pix->bytesperline =3D roundup(pix->width, 8); - pix->sizeimage =3D roundup(pix->width, 8) * pix->height * 3 / 2; - break; - } + pix->bytesperline =3D DIV_ROUND_UP(pix->width * bpp, 8); + pix->sizeimage =3D pix->bytesperline * pix->height; } =20 /* @@ -305,6 +293,7 @@ static void tegra20_channel_queue_setup(struct tegra_vi= _channel *chan) { unsigned int stride =3D chan->format.bytesperline; unsigned int height =3D chan->format.height; + unsigned int width =3D chan->format.width; =20 chan->start_offset =3D 0; =20 @@ -321,8 +310,8 @@ static void tegra20_channel_queue_setup(struct tegra_vi= _channel *chan) =20 case V4L2_PIX_FMT_YUV420: case V4L2_PIX_FMT_YVU420: - chan->addr_offset_u =3D stride * height; - chan->addr_offset_v =3D chan->addr_offset_u + stride * height / 4; + chan->addr_offset_u =3D width * height; + chan->addr_offset_v =3D chan->addr_offset_u + width * height / 4; =20 /* For YVU420, we swap the locations of the U and V planes. */ if (chan->format.pixelformat =3D=3D V4L2_PIX_FMT_YVU420) @@ -332,14 +321,14 @@ static void tegra20_channel_queue_setup(struct tegra_= vi_channel *chan) chan->start_offset_v =3D chan->addr_offset_v; =20 if (chan->vflip) { - chan->start_offset +=3D stride * (height - 1); - chan->start_offset_u +=3D (stride / 2) * ((height / 2) - 1); - chan->start_offset_v +=3D (stride / 2) * ((height / 2) - 1); + chan->start_offset +=3D width * (height - 1); + chan->start_offset_u +=3D (width / 2) * ((height / 2) - 1); + chan->start_offset_v +=3D (width / 2) * ((height / 2) - 1); } if (chan->hflip) { - chan->start_offset +=3D stride - 1; - chan->start_offset_u +=3D (stride / 2) - 1; - chan->start_offset_v +=3D (stride / 2) - 1; + chan->start_offset +=3D width - 1; + chan->start_offset_u +=3D (width / 2) - 1; + chan->start_offset_v +=3D (width / 2) - 1; } break; } @@ -576,20 +565,23 @@ static const struct tegra_vi_ops tegra20_vi_ops =3D { .vi_stop_streaming =3D tegra20_vi_stop_streaming, }; =20 -#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC) \ -{ \ - .code =3D MEDIA_BUS_FMT_##MBUS_CODE, \ - .bpp =3D BPP, \ - .fourcc =3D V4L2_PIX_FMT_##FOURCC, \ +#define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, FOURCC) \ +{ \ + .img_dt =3D TEGRA_IMAGE_DT_##DATA_TYPE, \ + .bit_width =3D BIT_WIDTH, \ + .code =3D MEDIA_BUS_FMT_##MBUS_CODE, \ + .bpp =3D BPP, \ + .fourcc =3D V4L2_PIX_FMT_##FOURCC, \ } =20 static const struct tegra_video_format tegra20_video_formats[] =3D { - TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY), - TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY), - TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV), - TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU), - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420), - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420), + /* YUV422 */ + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 16, UYVY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 16, VYUY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 16, YUYV), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YVYU), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420), }; =20 const struct tegra_vi_soc tegra20_vi_soc =3D { diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media= /tegra-video/vi.h index bfadde8858d4..5cbc0606ed6c 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -281,7 +281,8 @@ enum tegra_image_dt { * @img_dt: MIPI CSI-2 data type (for CSI-2 only) * @bit_width: format width in bits per component (for CSI/Tegra210 only) * @code: media bus format code - * @bpp: bytes per pixel (when stored in memory) + * @bpp: bytes per pixel (when stored in memory) for Tegra210, + * bits per pixel for Tegra20/Tegra30 * @img_fmt: image format (for CSI/Tegra210 only) * @fourcc: V4L2 pixel format FCC identifier */ --=20 2.48.1