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Thu, 25 Sep 2025 08:03:02 -0700 (PDT) From: Abel Vesa Date: Thu, 25 Sep 2025 18:02:49 +0300 Subject: [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250925-dts-qcom-glymur-crd-add-edp-v1-2-20233de3c1e2@linaro.org> References: <20250925-dts-qcom-glymur-crd-add-edp-v1-0-20233de3c1e2@linaro.org> In-Reply-To: <20250925-dts-qcom-glymur-crd-add-edp-v1-0-20233de3c1e2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Pankaj Patil , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=2567; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=cll6RmG9F61IQLZj7T9DX3710/Yd2WMaGJPdyftpPfs=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBo1Vmh04RbXZfHn66jfCKGqelW3BhZqin/x2fqj MGblcfCtoOJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaNVZoQAKCRAbX0TJAJUV VvoHEACNfmHVNfwTzSIdYaujbmfiD0TEAcMYhrXSgnY3tWe9PasX9h8T5BnzPZsz7JOwK24N4x8 KtEZ3qdPx7GCp494+BA/uiklxxDGiQLpGaTD0+lvDSxaDyF3raFA+3BTe+3FsVZG4C7fwepH5fr cScUobwBfjnj84vvnSJjqGY7hY8+VpTfAtVz8BWAobGK9gf6jDGrOZaiZT0loCs/6oTCmmOunXH 5Ui8ulOX3UDA5e91Jj3x3Pxfv2siBA9J+92WT4F/kPWURHeal2LKnhIaVALKGJAcmNM376j01NB RGRSciuwYXPcG484lH6Kl5KxSZ0SskxgFKVBqX2Xe7BEQBejDupPGBvREY0InZ2kwif62jlHVc6 UW/0i5MWJBwR4BEFTKjeHZt4XCjalKjQ6BzohEgkHKmr2Xfmh8u8czGNE6BD8M6k9tI6862Tdbj RQugZjLLiCbgCsWIqA0ThTPMLzuLqGUYM+7ldtv65ayjGlbNzyeUpuVbw+QjE3T4Cwsa0cYIYMh PiTNgeWtrTLUF5liuln/1NaTPDclGoyGRIDG9oC3k6vAW8AlvNnMPDvIzLzWWb4Tk+lPfKnqhJv icuwlJQt0/2kQqkJrgk+Mm6NAyBBqfuSHw+CtYA7jngJNym3Ru+jBfBuSlIGFt+7pLP17pa8rVp dWIYw97TqzRfNnA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Enable the MDSS (Mobile Display SubSystem) along with the 3rd DisplayPort controller and its PHY in order to bring support for the panel on Glymur CRD platform. Also describe the voltage regulator needed by the eDP panel. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 76 +++++++++++++++++++++++++++++= ++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 17c8f1a4f4061303982a210b7690783c96ef80b2..1d7e69a27612aea3bfdb2eedad4= 8d8bdb9e7dc8f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -172,6 +172,22 @@ pmic_glink_ss_in2: endpoint { }; }; =20 + vreg_edp_3p3: regulator-edp-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_EDP_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&edp_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible =3D "regulator-fixed"; =20 @@ -536,6 +552,52 @@ vreg_l4h_e0_1p2: ldo4 { }; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status =3D "okay"; + + aux-bus { + panel { + compatible =3D "samsung,atna60cl01", "samsung,atna33xc20"; + enable-gpios =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply =3D <&vreg_edp_3p3>; + + pinctrl-0 =3D <&edp_bl_en>; + pinctrl-names =3D "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint =3D <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + mdss_dp3_out: endpoint { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000= 00000>; + + remote-endpoint =3D <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply =3D <&vreg_l2f_e1_0p83>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + &pmk8850_rtc { no-alarm; }; @@ -570,6 +632,20 @@ &remoteproc_soccp { }; =20 &tlmm { + edp_bl_en: edp-bl-en-state { + pins =3D "gpio18"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins =3D "gpio70"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + pcie5_default: pcie5-default-state { clkreq-n-pins { pins =3D "gpio153"; --=20 2.48.1